Error when calling define targeting a child of a probe (backport #4175)…

… (#4176)

* Error when calling define targeting a child of a probe (#4175)

(cherry picked from commit 4de3581)

# Conflicts:
#	core/src/main/scala/chisel3/internal/package.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

core/src/main/scala/chisel3/internal/package.scala

@@ -132,6 +132,23 @@ package object internal {
     case leaf => leaf.probeInfo.nonEmpty
   }
 
+  private[chisel3] def requireNotChildOfProbe(
+    probe:        Data,
+    errorMessage: => String = ""
+  )(
+    implicit sourceInfo: SourceInfo
+  ): Unit = {
+    probe.binding match {
+      case Some(ChildBinding(parent)) =>
+        if (parent.probeInfo.nonEmpty) {
+          val providedMsg = errorMessage // only evaluate by-name argument once
+          val msg = if (providedMsg.isEmpty) "Expected a root of a probe." else providedMsg
+          Builder.error(msg)
+        }
+      case _ => ()
+    }
+  }
+
   // TODO this exists in cats.Traverse, should we just use that?
   private[chisel3] implicit class ListSyntax[A](xs: List[A]) {
     def mapAccumulate[B, C](z: B)(f: (B, A) => (B, C)): (B, List[C]) = {

core/src/main/scala/chisel3/probe/package.scala

@@ -37,6 +37,7 @@ package object probe extends SourceInfoDoc {
       Builder.error("Cannot define a probe on a non-equivalent type.")
     }
     requireHasProbeTypeModifier(sink, "Expected sink to be a probe.")
+    requireNotChildOfProbe(sink, "Expected sink to be the root of a probe.")
     requireHasProbeTypeModifier(probeExpr, "Expected source to be a probe expression.")
     if (sink.probeInfo.get.writable) {
       requireHasWritableProbeTypeModifier(

src/test/scala/chiselTests/ProbeSpec.scala

@@ -584,6 +584,22 @@ class ProbeSpec extends ChiselFlatSpec with Utils {
     exc.getMessage should include("Probe width unknown.")
   }
 
+  it should "error trying to define a child of an Aggregate probe" in {
+    val exc = intercept[chisel3.ChiselException] {
+      ChiselStage.emitSystemVerilog(
+        new RawModule {
+          val in = IO(Input(UInt(16.W)))
+          val p = IO(Output(Probe(new Bundle {
+            val a = UInt(16.W)
+          })))
+          define(p.a, ProbeValue(in))
+        },
+        Array("--throw-on-first-error")
+      )
+    }
+    exc.getMessage should include("Expected sink to be the root of a probe.")
+  }
+
   "Probe force/release reg example" should "work in simulator" in {
     // Simple example forcing a register and checking basic behavior.