-
Notifications
You must be signed in to change notification settings - Fork 592
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
add a lit demo to test SFC, firtool, panamaconverter in a same file
- Loading branch information
Showing
1 changed file
with
36 additions
and
8 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,17 +1,45 @@ | ||
| // RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" --java-opt="--enable-native-access=ALL-UNNAMED" --java-opt="--enable-preview" --java-opt="-Djava.library.path=%JAVALIBRARYPATH" %s | FileCheck %s | ||
| // RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" %s -- chirrtl | FileCheck %s -check-prefix=SFC-FIRRTL | ||
| // RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" %s -- chirrtl | firtool -format=fir | FileCheck %s -check-prefix=VERILOG | ||
| // RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" --java-opt="--enable-native-access=ALL-UNNAMED" --java-opt="--enable-preview" --java-opt="-Djava.library.path=%JAVALIBRARYPATH" %s -- panama-firrtl | FileCheck %s -check-prefix=MFC-FIRRTL | ||
| // RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" --java-opt="--enable-native-access=ALL-UNNAMED" --java-opt="--enable-preview" --java-opt="-Djava.library.path=%JAVALIBRARYPATH" %s -- panama-verilog | FileCheck %s -check-prefix=VERILOG | ||
|
|
||
| import chisel3._ | ||
| import lit.utility.panamaconverter._ | ||
|
|
||
| class FooBundle extends Bundle { | ||
| val foo = Input(UInt(3.W)) | ||
| } | ||
| // CHECK: circuit FooModule : | ||
| // CHECK: module FooModule : | ||
| // CHECK: input clock : Clock | ||
| // CHECK: input reset : UInt<1> | ||
|
|
||
| // SFC-FIRRTL-LABEL: circuit FooModule : | ||
| // SFC-FIRRTL-NEXT: module FooModule : | ||
| // SFC-FIRRTL-NEXT: input clock : Clock | ||
| // SFC-FIRRTL-NEXT: input reset : UInt<1> | ||
| // SFC-FIRRTL-NEXT: output io : { flip foo : UInt<3>} | ||
| // SFC-FIRRTL: skip | ||
|
|
||
| // MFC-FIRRTL-LABEL: circuit FooModule : | ||
| // MFC-FIRRTL-NEXT: module FooModule : | ||
| // MFC-FIRRTL-NEXT: input clock : Clock | ||
| // MFC-FIRRTL-NEXT: input reset : UInt<1> | ||
| // MFC-FIRRTL-NEXT: output io : { flip foo : UInt<3> } | ||
|
|
||
| // VERILOG-LABEL: module FooModule( | ||
| // VERILOG-NEXT: input clock, | ||
| // VERILOG-NEXT: reset, | ||
| // VERILOG-NEXT: input [2:0] io_foo | ||
| // VERILOG-NEXT: ); | ||
|
|
||
| class FooModule extends Module { | ||
| // CHECK: output io : { flip foo : UInt<3> } | ||
| val io = IO(new FooBundle) | ||
| } | ||
| print(firrtlString(new FooModule)) | ||
|
|
||
| args.head match { | ||
| case "chirrtl" => { | ||
| print(circt.stage.ChiselStage.emitCHIRRTL(new FooModule)) | ||
| } | ||
| case "panama-firrtl" => { | ||
| print(lit.utility.panamaconverter.firrtlString(new FooModule)) | ||
| } | ||
| case "panama-verilog" => { | ||
| print(lit.utility.panamaconverter.verilogString(new FooModule)) | ||
| } | ||
| } |