Resolve backport conflicts

chipsalliance · Apr 4, 2024 · 786844e · 786844e
1 parent 5921fc8
commit 786844e
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Showing 3 changed files with 3 additions and 39 deletions.
diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala
@@ -66,7 +66,7 @@ sealed abstract class Aggregate extends Data {
     */
   override def litValue: BigInt = {
     checkingLitOption(checkForDontCares = true).getOrElse(
-      throw new ChiselException(s"Cannot ask for litValue of $this as it is not a literal.")
+      throw new chisel3.ChiselException(s"Cannot ask for litValue of $this as it is not a literal.")
     )
   }
 

diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -822,12 +822,12 @@ private[chisel3] object Builder extends LazyLogging {
       val localTarget = view.toTarget
       val absTarget = view.toAbsoluteTarget
       val elts = getRecursiveFields.lazily(view, "").collect { case (elt: Element, _) => elt }
-      for (elt <- elts if !elt.isLit) {
+      for (elt <- elts) {
         // This is a hack to not crash when .viewAs is called on non-hardware
         // It can be removed in Chisel 6.0.0 when it becomes illegal to call .viewAs on non-hardware
         val targetOfViewOpt =
           try {
-            Some(reify(elt))
+            Some(reify(elt)).filterNot(_.isLit)
           } catch {
             case _: NoSuchElementException => None
           }

diff --git a/src/test/scala/chiselTests/experimental/DataView.scala b/src/test/scala/chiselTests/experimental/DataView.scala
@@ -928,41 +928,6 @@ class DataViewSpec extends ChiselFlatSpec {
     e.getMessage should include("View mapping must only contain Elements within the View")
   }
 
-<<<<<<< HEAD
-=======
-  it should "use the target in error messages involving the view" in {
-    val e1 = the[ChiselException] thrownBy (
-      ChiselStage.emitCHIRRTL(
-        new RawModule {
-          override def desiredName = "Top"
-          val in = IO(Input(UInt(8.W)))
-          val out = IO(Output(SInt(8.W)))
-          out.viewAs[SInt] := in
-        },
-        Array("--throw-on-first-error")
-      )
-    )
-    e1.getMessage should include(
-      "Connection between sink (Top.out: IO[SInt<8>]) and source (Top.in: IO[UInt<8>]) failed"
-    )
-
-    val e2 = the[ChiselException] thrownBy (
-      ChiselStage.emitCHIRRTL(
-        new RawModule {
-          override def desiredName = "Top"
-          val foo, bar = IO(Input(UInt(8.W)))
-          val fizz, buzz = IO(Output(SInt(8.W)))
-          // Unfortunately, := does a bad job when the view doesn't map to a single Data, but at least connectables do a good job
-          ((fizz, buzz).viewAs: Data) :#= ((foo, bar).viewAs: Data)
-        },
-        Array("--throw-on-first-error")
-      )
-    )
-    e2.getMessage should include(
-      "Connection between sink (Top.buzz: IO[SInt<8>]) and source (Top.bar: IO[UInt<8>]) failed"
-    )
-  }
-
   it should "preserve literal values for Elements" in {
     class MyModule extends Module {
       val x = 123.U
@@ -1034,7 +999,6 @@ class DataViewSpec extends ChiselFlatSpec {
     ChiselStage.emitCHIRRTL(new MyModule)
   }
 
->>>>>>> ce05462c2 (Support literals in DataView (#3964))
   behavior.of("PartialDataView")
 
   it should "still error if the mapping is non-total in the view" in {