Merge branch 'master' into 3.0.1

# Conflicts: # chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala # chiselFrontend/src/main/scala/chisel3/core/Module.scala # chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
chipsalliance · Dec 21, 2017 · 5cc147f · 5cc147f
2 parents 520fafe + e276571
commit 5cc147f
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Showing 3 changed files with 9 additions and 9 deletions.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -80,7 +80,7 @@ abstract class ExtModule(val params: Map[String, Param] = Map.empty[String, Para
     component
   }
 
-  private[core] def initializeInParent(instanceCompileOptions: CompileOptions): Unit = {
+  private[core] def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
     implicit val sourceInfo = UnlocatableSourceInfo
 
     for (x <- getModulePorts) {
@@ -165,7 +165,7 @@ abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param
     component
   }
 
-  private[core] def initializeInParent(instanceCompileOptions: CompileOptions): Unit = {
+  private[core] def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
     for ((_, port) <- io.elements) {
       pushCommand(DefInvalid(UnlocatableSourceInfo, port.ref))
     }

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -126,7 +126,7 @@ abstract class BaseModule extends HasId {
 
   /** Sets up this module in the parent context
     */
-  private[core] def initializeInParent(instanceCompileOptions: CompileOptions): Unit
+  private[core] def initializeInParent(parentCompileOptions: CompileOptions): Unit
 
   //
   // Chisel Internals

diff --git a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
@@ -81,10 +81,10 @@ abstract class UserModule(implicit moduleCompileOptions: CompileOptions)
     component
   }
 
-  private[core] def initializeInParent(instanceCompileOptions: CompileOptions): Unit = {
+  private[core] def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
     implicit val sourceInfo = UnlocatableSourceInfo
 
-    if (!instanceCompileOptions.explicitInvalidate) {
+    if (!parentCompileOptions.explicitInvalidate) {
       for (port <- getModulePorts) {
         pushCommand(DefInvalid(sourceInfo, port.ref))
       }
@@ -107,10 +107,10 @@ abstract class ImplicitModule(implicit moduleCompileOptions: CompileOptions)
   // Setup ClockAndReset
   Builder.currentClockAndReset = Some(ClockAndReset(clock, reset))
 
-  private[core] override def initializeInParent(instanceCompileOptions: CompileOptions): Unit = {
+  private[core] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
     implicit val sourceInfo = UnlocatableSourceInfo
 
-    super.initializeInParent(instanceCompileOptions)
+    super.initializeInParent(parentCompileOptions)
     clock := Builder.forcedClock
     reset := Builder.forcedReset
   }
@@ -176,12 +176,12 @@ abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions)
     super.generateComponent()
   }
 
-  private[core] override def initializeInParent(instanceCompileOptions: CompileOptions): Unit = {
+  private[core] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
     // Don't generate source info referencing parents inside a module, since this interferes with
     // module de-duplication in FIRRTL emission.
     implicit val sourceInfo = UnlocatableSourceInfo
 
-    if (!instanceCompileOptions.explicitInvalidate) {
+    if (!parentCompileOptions.explicitInvalidate) {
       pushCommand(DefInvalid(sourceInfo, io.ref))
     }