Don't emit nodes when calling .asBool on a Bool (backport #3637) (#3639)

* Don't emit nodes when calling .asBool on a Bool

(cherry picked from commit d5e65a3)

# Conflicts:
#	src/test/scala/chiselTests/LTLSpec.scala
#	src/test/scala/chiselTests/VerificationSpec.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

core/src/main/scala/chisel3/Bits.scala

@@ -396,7 +396,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi
   /** @group SourceInfoTransformMacro */
   def do_asSInt(implicit sourceInfo: SourceInfo): SInt
 
-  final def do_asBool(implicit sourceInfo: SourceInfo): Bool = {
+  def do_asBool(implicit sourceInfo: SourceInfo): Bool = {
     width match {
       case KnownWidth(1) => this(0)
       case _             => throwException(s"can't covert ${this.getClass.getSimpleName}$width to Bool")
@@ -1203,6 +1203,8 @@ sealed class Bool() extends UInt(1.W) with Reset {
   /** @group SourceInfoTransformMacro */
   def do_&&(that: Bool)(implicit sourceInfo: SourceInfo): Bool = this & that
 
+  override def do_asBool(implicit sourceInfo: SourceInfo): Bool = this
+
   /** Reinterprets this $coll as a clock */
   def asClock: Clock = macro SourceInfoTransform.noArg
 

src/test/scala/chiselTests/UIntOps.scala

@@ -463,4 +463,20 @@ class UIntOpsSpec extends ChiselPropSpec with Matchers with Utils {
         log should be("")
     }
   }
+
+  property("Calling .asBool on a Bool should be a noop") {
+    val chirrtl = ChiselStage.emitCHIRRTL(new RawModule {
+      val a = IO(Input(Bool()))
+      val b: UInt = IO(Input(Bool()))
+      val y, z = IO(Output(Bool()))
+      val c = a.asBool
+      val d = b.asBool
+      y := c
+      z := d
+      a should be(c)
+      b should be(d)
+    })
+    chirrtl should include("y <= a")
+    chirrtl should include("z <= b")
+  }
 }

src/test/scala/chiselTests/VerificationSpec.scala

@@ -33,14 +33,14 @@ class VerificationSpec extends ChiselPropSpec with Matchers {
     val lines = fir.split("\n").map(_.trim).toIndexedSeq
 
     // reset guard around the verification statement
-    assertContains(lines, "when _T_2 : ")
+    assertContains(lines, "when _T_1 : ")
     assertContains(lines, "cover(clock, _T, UInt<1>(\"h1\"), \"\")")
 
-    assertContains(lines, "when _T_6 : ")
-    assertContains(lines, "assume(clock, _T_4, UInt<1>(\"h1\"), \"\")")
+    assertContains(lines, "when _T_5 : ")
+    assertContains(lines, "assume(clock, _T_3, UInt<1>(\"h1\"), \"\")")
 
-    assertContains(lines, "when _T_10 : ")
-    assertContains(lines, "assert(clock, _T_8, UInt<1>(\"h1\"), \"\")")
+    assertContains(lines, "when _T_8 : ")
+    assertContains(lines, "assert(clock, _T_6, UInt<1>(\"h1\"), \"\")")
   }
 
   property("annotation of verification constructs should work") {