Updates

chipsalliance · Jul 21, 2022 · 1d39d26 · 1d39d26
1 parent ea028f9
commit 1d39d26
Show file tree

Hide file tree

Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
@@ -83,7 +83,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends
               case MemoryPortBinding(_, _) =>
                 id.forceName(default = "MPORT", _namespace)
               case PortBinding(_) =>
-                id.forceName(None, default = "PORT", _namespace, true, x => ModuleIO(this, x))
+                id.forceName(default = "PORT", _namespace, true, x => ModuleIO(this, x))
               case RegBinding(_, _) =>
                 id.forceName(default = "REG", _namespace)
               case WireBinding(_, _) =>

diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -192,14 +192,13 @@ private[chisel3] trait HasId extends InstanceId {
   // Will not do any naming if the reference already assigned.
   // (e.g. tried to suggest a name to part of a Record)
   private[chisel3] def forceName(
-    prefix:     Option[String],
     default:    => String,
     namespace:  Namespace,
     errorIfDup: Boolean = false,
     refBuilder: String => Arg = Ref(_)
   ): Unit =
     if (_ref.isEmpty) {
-      val candidate_name = _computeName(prefix, Some(default).filterNot(_ => errorIfDup)).get
+      val candidate_name = _computeName(Some(default).filterNot(_ => errorIfDup)).get
       val available_name = namespace.name(candidate_name)
       println(s"candidate: $candidate_name, available: $available_name")
       if (errorIfDup && (available_name != candidate_name)) {
@@ -209,6 +208,7 @@ private[chisel3] trait HasId extends InstanceId {
       // Clear naming prefix to free memory
       naming_prefix = Nil
     }
+
   private var _ref: Option[Arg] = None
   private[chisel3] def setRef(imm: Arg): Unit = setRef(imm, false)
   private[chisel3] def setRef(imm: Arg, force: Boolean): Unit = {