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User/dev/michnorris/jtag port fix main #425

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merged 2 commits into from
Feb 26, 2024
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Merged

User/dev/michnorris/jtag port fix main #425

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f93f57b
porting tdo enable from jtag controller up to top level interface
Feb 20, 2024
0572a90
updating top level testbench for uvm
Feb 20, 2024
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4 changes: 3 additions & 1 deletion src/integration/rtl/caliptra_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,7 @@ module caliptra_top
input logic jtag_tdi, // JTAG tdi
input logic jtag_trst_n, // JTAG Reset
output logic jtag_tdo, // JTAG TDO
output logic jtag_tdoEn, // JTAG TDO enable

//APB Interface
input logic [`CALIPTRA_APB_ADDR_WIDTH-1:0] PADDR,
Expand Down Expand Up @@ -492,8 +493,9 @@ el2_veer_wrapper rvtop (
.jtag_tck ( jtag_tck ),
.jtag_tms ( jtag_tms ),
.jtag_tdi ( jtag_tdi ),
.jtag_trst_n ( jtag_trst_n ),
.jtag_trst_n ( jtag_trst_n ),
.jtag_tdo ( jtag_tdo ),
.jtag_tdoEn ( jtag_tdoEn ),

//caliptra uncore jtag ports
.cptra_uncore_dmi_reg_en ( cptra_uncore_dmi_reg_en ),
Expand Down
2 changes: 2 additions & 0 deletions src/integration/tb/caliptra_top_tb.sv
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Expand Up @@ -111,6 +111,7 @@ module caliptra_top_tb (
logic jtag_tdi; // JTAG tdi
logic jtag_trst_n; // JTAG Reset
logic jtag_tdo; // JTAG TDO
logic jtag_tdoEn; // JTAG TDO enable
//APB Interface
logic [`CALIPTRA_APB_ADDR_WIDTH-1:0] PADDR;
logic [2:0] PPROT;
Expand Down Expand Up @@ -1079,6 +1080,7 @@ caliptra_top caliptra_top_dut (
.jtag_tms(jtag_tms),
.jtag_trst_n(jtag_trst_n),
.jtag_tdo(jtag_tdo),
.jtag_tdoEn(jtag_tdoEn),

.PADDR(PADDR),
.PPROT(PPROT),
Expand Down
2 changes: 2 additions & 0 deletions ...mf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv
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Expand Up @@ -108,6 +108,7 @@ import uvmf_base_pkg_hdl::*;
logic jtag_tdi = '0; // JTAG tdi
logic jtag_trst_n = '0; // JTAG Reset
logic jtag_tdo; // JTAG TDO
logic jtag_tdoEn; // JTAG TDO enable

mbox_sram_req_t mbox_sram_req;
mbox_sram_resp_t mbox_sram_resp;
Expand Down Expand Up @@ -196,6 +197,7 @@ import uvmf_base_pkg_hdl::*;
.jtag_tms (jtag_tms ),
.jtag_trst_n(jtag_trst_n),
.jtag_tdo (jtag_tdo ),
.jtag_tdoEn (jtag_tdoEn ),

.PADDR (uvm_test_top_environment_soc_ifc_subenv_qvip_apb5_slave_subenv_qvip_hdl.apb5_master_0_PADDR ),
.PPROT (3'b000/*FIXME*/ ),
Expand Down
6 changes: 3 additions & 3 deletions src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
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Expand Up @@ -305,7 +305,8 @@ import soc_ifc_pkg::*;
input logic jtag_tdi, // JTAG tdi
input logic jtag_trst_n, // JTAG Reset
output logic jtag_tdo, // JTAG TDO

output logic jtag_tdoEn, // JTAG Test Data Output enable

//caliptra uncore jtag ports
output logic cptra_uncore_dmi_reg_en,
output logic cptra_uncore_dmi_reg_wr_en,
Expand Down Expand Up @@ -404,7 +405,6 @@ import soc_ifc_pkg::*;
logic [77:0] iccm_rd_data_ecc;

logic core_rst_l; // Core reset including rst_l and dbg_rst_l
logic jtag_tdoEn;

logic dccm_clk_override;
logic icm_clk_override;
Expand Down Expand Up @@ -719,7 +719,7 @@ import soc_ifc_pkg::*;
.tms (jtag_tms), // Test mode select
.tdi (jtag_tdi), // Test Data Input
.tdo (jtag_tdo), // Test Data Output
.tdoEnable (),
.tdoEnable (jtag_tdoEn), // Test Data Output enable
// Processor Signals
.core_rst_n (dbg_rst_l), // Debug reset, active low
.core_clk (clk), // Core clock
Expand Down
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