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Merge pull request #3993 from alainmarcel/alainmarcel-patch-1
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import package item fix for synlig
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@alaindargelas
alaindargelas authored Oct 3, 2024
2 parents c0cdf5f + 6a4fa76 commit 9c3c533
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Showing 32 changed files with 3,618 additions and 82 deletions.
19 changes: 19 additions & 0 deletions .vscode/launch.json
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Original file line number Diff line number Diff line change
Expand Up @@ -889,6 +889,25 @@
}
]
},
{
"name": "ScratchPad_NoUHDMElab",
"type": "cppdbg",
"request": "launch",
"program": "${workspaceFolder}/dbuild/bin/surelog",
"args": ["-parse", "tests/ScratchPad.sv", "-d", "inst", "-synth", "-d", "ast", "-d", "uhdm", "-d", "uhdmstats", "-d", "vpi_ids", "-replay", "-nobuiltin"],
"stopAtEntry": false,
"cwd": "${workspaceFolder}",
"environment": [],
"externalConsole": false,
"MIMode": "gdb",
"setupCommands": [
{
"description": "Enable pretty-printing for gdb",
"text": "-enable-pretty-printing",
"ignoreFailures": true
}
]
},
{
"name": "ScratchPad_v",
"type": "cppdbg",
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1 change: 1 addition & 0 deletions include/Surelog/DesignCompile/UhdmWriter.h
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Original file line number Diff line number Diff line change
Expand Up @@ -84,6 +84,7 @@ class UhdmWriter final {
void writeDataTypes(const DesignComponent::DataTypeMap& datatypeMap,
UHDM::BaseClass* parent, UHDM::VectorOftypespec* dest_typespecs,
UHDM::Serializer& s, bool setParent);
void writeImportedSymbols(DesignComponent* mod, UHDM::Serializer& s, UHDM::VectorOftypespec* typespecs);
void writeVariables(const DesignComponent::VariableMap& orig_vars,
UHDM::BaseClass* parent,
UHDM::VectorOfvariables* dest_vars, UHDM::Serializer& s);
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143 changes: 118 additions & 25 deletions src/DesignCompile/UhdmWriter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1075,12 +1075,10 @@ void UhdmWriter::writePackage(Package* pack, package* p, Serializer& s,
VectorOftypespec* typespecs = s.MakeTypespecVec();
p->Typespecs(typespecs);
writeDataTypes(pack->getDataTypeMap(), p, typespecs, s, true);
writeImportedSymbols(pack, s, typespecs);
for (auto tp : *typespecs) {
tp->Instance(p);
}
for (auto item : pack->getImportedSymbols()) {
typespecs->push_back(item);
}
// Classes
ClassNameClassDefinitionMultiMap& orig_classes = pack->getClassDefinitions();
dest_classes = s.MakeClass_defnVec();
Expand Down Expand Up @@ -1194,6 +1192,101 @@ void UhdmWriter::writePackage(Package* pack, package* p, Serializer& s,
lateBinding(s, pack, p);
}

void UhdmWriter::writeImportedSymbols(DesignComponent* mod, Serializer& s,
VectorOftypespec* typespecs) {
for (auto item : mod->getImportedSymbols()) {
bool append = true;
for (auto tpsiter : *typespecs) {
if (item->VpiName() == tpsiter->VpiName()) {
append = false;
break;
}
}
if (append) { // Prevents multiple definition
typespecs->push_back(item);
}
constant* c = item->Item();
if (c) {
std::string_view packName = item->VpiName();
std::string_view typeName = c->VpiDecompile();
Package* pack =
m_compileDesign->getCompiler()->getDesign()->getPackage(packName);
if (pack) {
const auto& itr = m_componentMap.find(pack);
if (itr != m_componentMap.end()) {
package* p = (package*)itr->second;
typespec* tps = nullptr;
enum_const* cts = nullptr;
if (p->Typespecs()) {
for (auto n : *p->Typespecs()) {
if (n->VpiName() == typeName) {
tps = n;
break;
}
const std::string pname = StrCat(p->VpiName(), "::", typeName);
if (n->VpiName() == pname) {
tps = n;
break;
}
if (n->UhdmType() == uhdmenum_typespec) {
enum_typespec* tpsiter = any_cast<enum_typespec*>(n);
if (tpsiter && tpsiter->Enum_consts()) {
for (auto c : *tpsiter->Enum_consts()) {
if (c->VpiName() == typeName) {
cts = c;
tps = tpsiter;
break;
}
if (pname == c->VpiName()) {
cts = c;
tps = tpsiter;
break;
}
}
}
}
if (cts) break;
}
}
if (cts) {
// Ideally we would want to import only the given symbol,
// But Synlig does not process that properly, so instead we import
// the whole enum
bool append = true;
for (auto tpsiter : *typespecs) {
if (tps->VpiName() == tpsiter->VpiName()) {
append = false;
break;
}
}
if (append) { // Prevents multiple definition
ElaboratorContext elaboratorContext(&s, false, true);
typespec* item =
(typespec*)UHDM::clone_tree(tps, &elaboratorContext);
typespecs->push_back(item);
}
} else if (tps) {
bool append = true;
for (auto tpsiter : *typespecs) {
if (tps->VpiName() == tpsiter->VpiName()) {
append = false;
break;
}
}
if (append) { // Prevents multiple definition
ElaboratorContext elaboratorContext(&s, false, true);
typespec* item =
(typespec*)UHDM::clone_tree(tps, &elaboratorContext);
item->VpiName(typeName);
typespecs->push_back(item);
}
}
}
}
}
}
}

void UhdmWriter::writeModule(ModuleDefinition* mod, module_inst* m,
Serializer& s, ModuleMap& moduleMap,
ModPortMap& modPortMap, ModuleInstance* instance) {
Expand Down Expand Up @@ -1240,9 +1333,7 @@ void UhdmWriter::writeModule(ModuleDefinition* mod, module_inst* m,
VectorOftypespec* typespecs = s.MakeTypespecVec();
m->Typespecs(typespecs);
writeDataTypes(mod->getDataTypeMap(), m, typespecs, s, true);
for (auto item : mod->getImportedSymbols()) {
typespecs->push_back(item);
}
writeImportedSymbols(mod, s, typespecs);
// Ports
std::vector<Signal*>& orig_ports = mod->getPorts();
VectorOfport* dest_ports = s.MakePortVec();
Expand Down Expand Up @@ -1465,9 +1556,7 @@ void UhdmWriter::writeInterface(ModuleDefinition* mod, interface_inst* m,
VectorOftypespec* typespecs = s.MakeTypespecVec();
m->Typespecs(typespecs);
writeDataTypes(mod->getDataTypeMap(), m, typespecs, s, true);
for (auto item : mod->getImportedSymbols()) {
typespecs->push_back(item);
}
writeImportedSymbols(mod, s, typespecs);
// Ports
std::vector<Signal*>& orig_ports = mod->getPorts();
VectorOfport* dest_ports = s.MakePortVec();
Expand Down Expand Up @@ -1604,9 +1693,7 @@ void UhdmWriter::writeProgram(Program* mod, program* m, Serializer& s,
VectorOftypespec* typespecs = s.MakeTypespecVec();
m->Typespecs(typespecs);
writeDataTypes(mod->getDataTypeMap(), m, typespecs, s, true);
for (auto item : mod->getImportedSymbols()) {
typespecs->push_back(item);
}
writeImportedSymbols(mod, s, typespecs);
// Ports
std::vector<Signal*>& orig_ports = mod->getPorts();
VectorOfport* dest_ports = s.MakePortVec();
Expand Down Expand Up @@ -1732,9 +1819,7 @@ bool UhdmWriter::writeElabProgram(Serializer& s, ModuleInstance* instance,
VectorOftypespec* typespecs = s.MakeTypespecVec();
m->Typespecs(typespecs);
writeDataTypes(mod->getDataTypeMap(), m, typespecs, s, false);
for (auto item : mod->getImportedSymbols()) {
typespecs->push_back(item);
}
writeImportedSymbols(mod, s, typespecs);
// Assertions
if (mod->getAssertions()) {
m->Assertions(mod->getAssertions());
Expand Down Expand Up @@ -2137,9 +2222,7 @@ bool UhdmWriter::writeElabGenScope(Serializer& s, ModuleInstance* instance,
VectorOftypespec* typespecs = s.MakeTypespecVec();
m->Typespecs(typespecs);
writeDataTypes(mod->getDataTypeMap(), m, typespecs, s, true);
for (auto item : mod->getImportedSymbols()) {
typespecs->push_back(item);
}
writeImportedSymbols(mod, s, typespecs);
// System elab tasks
m->Elab_tasks((std::vector<UHDM::tf_call*>*)&mod->getElabSysCalls());
if (m->Elab_tasks()) {
Expand Down Expand Up @@ -3606,7 +3689,9 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
const any* lhs = p->Lhs();
if (lhs->VpiName() == name) {
// Do not bind blindly here, let the uhdmelab do this correctly
// ref->Actual_group((any*)p->Rhs());
// Unless we are in a package
if (m && m->UhdmType() == uhdmpackage)
ref->Actual_group((any*)p->Rhs());
isParam = true;
break;
}
Expand Down Expand Up @@ -3736,6 +3821,18 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
}
}

if (!ref->Actual_group()) {
Value* value = mod->getValue(name);
if (value && value->isValid()) {
enum_const* c = s.MakeEnum_const();
c->VpiName(name);
c->VpiValue(value->uhdmValue());
c->VpiDecompile(value->decompiledValue());
c->VpiSize(value->getSize());
c->VpiParent(ref);
ref->Actual_group(c);
}
}
if (!ref->Actual_group()) {
if (mod) {
if (auto elem = mod->getDesignElement()) {
Expand Down Expand Up @@ -3813,9 +3910,7 @@ bool UhdmWriter::writeElabModule(Serializer& s, ModuleInstance* instance,
VectorOftypespec* typespecs = s.MakeTypespecVec();
m->Typespecs(typespecs);
writeDataTypes(mod->getDataTypeMap(), m, typespecs, s, false);
for (auto item : mod->getImportedSymbols()) {
typespecs->push_back(item);
}
writeImportedSymbols(mod, s, typespecs);
// System elab tasks
m->Elab_tasks((std::vector<UHDM::tf_call*>*)&mod->getElabSysCalls());
if (m->Elab_tasks()) {
Expand Down Expand Up @@ -3963,9 +4058,7 @@ bool UhdmWriter::writeElabInterface(Serializer& s, ModuleInstance* instance,
VectorOftypespec* typespecs = s.MakeTypespecVec();
m->Typespecs(typespecs);
writeDataTypes(mod->getDataTypeMap(), m, typespecs, s, false);
for (auto item : mod->getImportedSymbols()) {
typespecs->push_back(item);
}
writeImportedSymbols(mod, s, typespecs);
// System elab tasks
m->Elab_tasks((std::vector<UHDM::tf_call*>*)&mod->getElabSysCalls());
if (m->Elab_tasks()) {
Expand Down
4 changes: 2 additions & 2 deletions tests/AssignSubs/AssignSubs.log
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Original file line number Diff line number Diff line change
Expand Up @@ -187,7 +187,7 @@ begin 3
bit_select 2
constant 27
design 1
enum_const 2
enum_const 3
enum_typespec 2
event_control 2
gen_for 1
Expand Down Expand Up @@ -220,7 +220,7 @@ begin 4
bit_select 3
constant 27
design 1
enum_const 2
enum_const 3
enum_typespec 2
event_control 3
gen_for 1
Expand Down
2 changes: 0 additions & 2 deletions tests/BlockingAssignRewrite/BlockingAssignRewrite.log
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Expand Up @@ -1023,8 +1023,6 @@ ref_obj 106
ref_typespec 95
ref_var 2
=== UHDM Object Stats End ===
Converting blocking to non-blocking assignment to enable RAM inference for RAM
Converting blocking to non-blocking assignment to enable RAM inference for RAM
[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/BlockingAssignRewrite/slpp_all/surelog.uhdm ...
[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/BlockingAssignRewrite/slpp_all/checker/surelog.chk.html ...
[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/BlockingAssignRewrite/slpp_all/surelog.uhdm ...
Expand Down
2 changes: 1 addition & 1 deletion tests/EarlgreyPackParam/EarlgreyPackParam.log
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Expand Up @@ -2351,5 +2351,5 @@ design: (work@test)
[ NOTE] : 7

============================== Begin RoundTrip Results ==============================
[roundtrip]: ${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv | ${SURELOG_DIR}/build/regression/EarlgreyPackParam/roundtrip/dut_000.sv | 27 | 60 |
[roundtrip]: ${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv | ${SURELOG_DIR}/build/regression/EarlgreyPackParam/roundtrip/dut_000.sv | 28 | 60 |
============================== End RoundTrip Results ==============================
2 changes: 1 addition & 1 deletion tests/EnumConstConcat/EnumConstConcat.log
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Original file line number Diff line number Diff line change
Expand Up @@ -622,5 +622,5 @@ design: (work@top)
[ NOTE] : 5

============================== Begin RoundTrip Results ==============================
[roundtrip]: ${SURELOG_DIR}/tests/EnumConstConcat/dut.sv | ${SURELOG_DIR}/build/regression/EnumConstConcat/roundtrip/dut_000.sv | 3 | 28 |
[roundtrip]: ${SURELOG_DIR}/tests/EnumConstConcat/dut.sv | ${SURELOG_DIR}/build/regression/EnumConstConcat/roundtrip/dut_000.sv | 4 | 28 |
============================== End RoundTrip Results ==============================
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