Add trigger logic tests in LSU

[kiryk]

The PR extends verification tests of LSU. A similar test was already used in DEC.

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	input logic [31:0] lsu_addr_m, // address
	input logic [31:0] store_data_m, // store data
	input logic [31:0] lsu_addr_m, // address
	input logic [31:0] store_data_m, // store data

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	output logic [3:0] lsu_trigger_match_m // match result
	output logic [3:0] lsu_trigger_match_m // match result

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	assign lsu_pkt_m.word = 1; // lsu_word;
	assign lsu_pkt_m.half = 1; // lsu_half;
	assign lsu_pkt_m.dma = 0; // lsu_dma;
	assign lsu_pkt_m.valid = 1; // lsu_valid;
	assign lsu_pkt_m.store = 1; // lsu_store;
	assign lsu_pkt_m.word = 1; // lsu_word;
	assign lsu_pkt_m.half = 1; // lsu_half;
	assign lsu_pkt_m.dma = 0; // lsu_dma;
	assign lsu_pkt_m.valid = 1; // lsu_valid;
	assign lsu_pkt_m.store = 1; // lsu_store;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	el2_lsu_trigger tu (
	.*
	);
	el2_lsu_trigger tu (.*);

[github-actions]

Links to coverage and verification reports for this PR (#224) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

[github-actions]

Links to coverage and verification reports for this PR (#224) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

[tmichalak]

LGTM