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urtl
urtl
 
 
Arty-A7-100-Master.xdc
Arty-A7-100-Master.xdc
 
 
Arty-A7-35-Master.xdc
Arty-A7-35-Master.xdc
 
 
README.md
README.md
 
 
clk_counter.v
clk_counter.v
 
 
clk_div.v
clk_div.v
 
 
default.hex
default.hex
 
 
default_even.hex
default_even.hex
 
 
default_odd.hex
default_odd.hex
 
 
fpga_leds.v
fpga_leds.v
 
 
fpga_top.v
fpga_top.v
 
 
fpga_top.xdc
fpga_top.xdc
 
 
output_port.v
output_port.v
 
 
soc_top.v
soc_top.v
 
 
soc_top_gtr.v
soc_top_gtr.v
 
 
soc_top_r.v
soc_top_r.v
 
 
syncram_8bit.v
syncram_8bit.v
 
 
syncram_dp_8bit.v
syncram_dp_8bit.v
 
 
t6551.v
t6551.v
 
 
t6551_rx.v
t6551_rx.v
 
 
t6551_tx.v
t6551_tx.v
 
 
turbo9.v
turbo9.v
 
 
turbo9_address_alu.v
turbo9_address_alu.v
 
 
turbo9_ccr.v
turbo9_ccr.v
 
 
turbo9_data_alu.v
turbo9_data_alu.v
 
 
turbo9_data_mem_ctrl.v
turbo9_data_mem_ctrl.v
 
 
turbo9_decode_stage.v
turbo9_decode_stage.v
 
 
turbo9_execute_stage.v
turbo9_execute_stage.v
 
 
turbo9_fetch_queue.v
turbo9_fetch_queue.v
 
 
turbo9_fetch_stage.v
turbo9_fetch_stage.v
 
 
turbo9_fifo_8x4.v
turbo9_fifo_8x4.v
 
 
turbo9_fifo_8x8.v
turbo9_fifo_8x8.v
 
 
turbo9_gtr.v
turbo9_gtr.v
 
 
turbo9_instr_format_decode.v
turbo9_instr_format_decode.v
 
 
turbo9_microsequencer.v
turbo9_microsequencer.v
 
 
turbo9_pipeline.v
turbo9_pipeline.v
 
 
turbo9_r.v
turbo9_r.v
 
 
turbo9_reg_addr_ctrl.v
turbo9_reg_addr_ctrl.v
 
 
turbo9_register_array.v
turbo9_register_array.v
 
 
turbo9_seq_arithmetic_unit.mul.v
turbo9_seq_arithmetic_unit.mul.v
 
 
turbo9_seq_arithmetic_unit.non_restore.v
turbo9_seq_arithmetic_unit.non_restore.v
 
 
turbo9_seq_arithmetic_unit.v
turbo9_seq_arithmetic_unit.v
 
 
turbo9_uop_generator.v
turbo9_uop_generator.v
 
 
turbo9_urtl_decode_pg1_AR.v
turbo9_urtl_decode_pg1_AR.v
 
 
turbo9_urtl_decode_pg1_JTA.v
turbo9_urtl_decode_pg1_JTA.v
 
 
turbo9_urtl_decode_pg1_JTB.v
turbo9_urtl_decode_pg1_JTB.v
 
 
turbo9_urtl_decode_pg1_R1.v
turbo9_urtl_decode_pg1_R1.v
 
 
turbo9_urtl_decode_pg1_R2.v
turbo9_urtl_decode_pg1_R2.v
 
 
turbo9_urtl_decode_pg2_AR.v
turbo9_urtl_decode_pg2_AR.v
 
 
turbo9_urtl_decode_pg2_JTA.v
turbo9_urtl_decode_pg2_JTA.v
 
 
turbo9_urtl_decode_pg2_JTB.v
turbo9_urtl_decode_pg2_JTB.v
 
 
turbo9_urtl_decode_pg2_R1.v
turbo9_urtl_decode_pg2_R1.v
 
 
turbo9_urtl_decode_pg2_R2.v
turbo9_urtl_decode_pg2_R2.v
 
 
turbo9_urtl_decode_pg3_AR.v
turbo9_urtl_decode_pg3_AR.v
 
 
turbo9_urtl_decode_pg3_JTA.v
turbo9_urtl_decode_pg3_JTA.v
 
 
turbo9_urtl_decode_pg3_JTB.v
turbo9_urtl_decode_pg3_JTB.v
 
 
turbo9_urtl_decode_pg3_R1.v
turbo9_urtl_decode_pg3_R1.v
 
 
turbo9_urtl_decode_pg3_R2.v
turbo9_urtl_decode_pg3_R2.v
 
 
turbo9_urtl_microcode.v
turbo9_urtl_microcode.v
 
 
turbo9_wishbone_2x8bit.v
turbo9_wishbone_2x8bit.v
 
 
turbo9_wishbone_8bit.v
turbo9_wishbone_8bit.v
 
 

README.md

Top Level Files
fpga_top.v FPGA top
soc_top.v SoC top 8-bit memory bus
soc_top_r.v SoC top 16-bit memory bus
soc_top_gtr.v SoC top 16-bit Harvard memory bus
turbo9.v Turbo9 top 8-bit memory bus
turbo9_r.v Turbo9 top 16-bit memory bus
turbo9_gtr.v Turbo9 top 16-bit Harvard memory bus