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Try to compile an ishl instruction with an i8 lhs and i128 rhs using the x64 backend.
Expected Results
It compiles.
Actual Results
Panics with thread 'rustc' panicked at 'Multi-register value not expected', /home/bjorn/.cargo/git/checkouts/wasmtime-41807828cb3a7a7e/c07ec4c/cranelift/codegen/src/isa/x64/lower.rs:128:10
The text was updated successfully, but these errors were encountered:
bjorn3
added
bug
Incorrect behavior in the current implementation that needs fixing
cranelift
Issues related to the Cranelift code generator
labels
Feb 21, 2021
cfallin
added a commit
to cfallin/wasmtime
that referenced
this issue
Feb 23, 2021
This fixesbytecodealliance#2672 and bytecodealliance#2679, and also fixes an incorrect instruction
emission (`test` with small immediate) that we had missed earlier.
The shift-related fixes have to do with (i) shifts by 0 bits, as a
special case that must be handled; and (ii) shifts by a 128-bit amount,
which we can handle by just dropping the upper half (we only use 3--7
bits of shift amount).
This adjusts the lowerings appropriately, and also adds run-tests to
ensure that the lowerings actually execute correctly (previously we only
had compile-tests with golden lowerings; I'd like to correct this for
more ops eventually, adding run-tests beyond what the Wasm spec and
frontend covers).
Steps to Reproduce
Try to compile an
ishl
instruction with ani8
lhs andi128
rhs using the x64 backend.Expected Results
It compiles.
Actual Results
Panics with
thread 'rustc' panicked at 'Multi-register value not expected', /home/bjorn/.cargo/git/checkouts/wasmtime-41807828cb3a7a7e/c07ec4c/cranelift/codegen/src/isa/x64/lower.rs:128:10
Versions and Environment
Cranelift version or commit: c07ec4c
Operating system: N/A
Architecture: x86_64
The text was updated successfully, but these errors were encountered: