Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Add bswap instruction #1092

Closed
bjorn3 opened this issue Jun 11, 2019 · 3 comments
Closed

Add bswap instruction #1092

bjorn3 opened this issue Jun 11, 2019 · 3 comments
Labels
cranelift:area:clif cranelift:goal:rustc Focus area: Support for compiling Rust! cranelift Issues related to the Cranelift code generator enhancement

Comments

@bjorn3
Copy link
Contributor

bjorn3 commented Jun 11, 2019

There is an x86 instruction for this.
@bjorn3 bjorn3 changed the title bswap Add bswap instruction Jun 11, 2019
@alexcrichton alexcrichton transferred this issue from bytecodealliance/cranelift Feb 28, 2020
@alexcrichton alexcrichton added cranelift:goal:rustc Focus area: Support for compiling Rust! cranelift Issues related to the Cranelift code generator labels Feb 28, 2020
@scottmcm scottmcm mentioned this issue May 31, 2021
Merged
11evan added a commit to 11evan/wasmtime that referenced this issue Oct 18, 2022
@11evan
big ole WIP: Add Bswap instruction to IR and implement in x64 (byteco…
f4509d3 
…dealliance#1092)

Adds Bswap to the Cranelift IR. Implements the Bswap instruction
in the x64 codegen backend (32 and 64 bit).

Does not implement Bswap for aarch64 or s390x, and also does not
handle 16-bit bswap in x64 (which requires a different instruction,
XCHG). Those are left for future commits.
11evan added a commit to 11evan/wasmtime that referenced this issue Oct 24, 2022
@11evan
Add Bswap instruction to IR and implement in x64 (bytecodealliance#1092)
dc88800 
Adds Bswap to the Cranelift IR. Implements the Bswap instruction
in the x64 codegen backend (32 and 64 bit).

Does not implement Bswap for aarch64 or s390x, and also does not
handle 16-bit bswap in x64 (which requires a different instruction,
XCHG). Those are left for future commits.

The x64 implementation for emitting Bswap follows the pattern
set by similar instrutions like Neg and Not - it only operates
on a dst register, but we parameterize it with both a src and
dst which are expected to be the same register.
11evan added a commit to 11evan/wasmtime that referenced this issue Oct 25, 2022
@11evan
WIP Implement Bswap instruction in aarch64 (bytecodealliance#1092)
3a88f26
11evan added a commit to 11evan/wasmtime that referenced this issue Oct 25, 2022
@11evan
WIP Implement Bswap instruction in aarch64 (bytecodealliance#1092)
62c26e3 
Turns Cranelift IR Bswap into arm64 rev16, rev32,
or rev64 instruction as appropriate
11evan added a commit to 11evan/wasmtime that referenced this issue Oct 26, 2022
@11evan
Implement Bswap instruction in aarch64 (bytecodealliance#1092)
ec502b5 
Turns Cranelift IR Bswap into arm64 rev16, rev32,
or rev64 instruction as appropriate
11evan added a commit to 11evan/wasmtime that referenced this issue Oct 26, 2022
@11evan
Implement x64 16-bit bswap with rol (bytecodealliance#1092)
e1f1dde 
x64 bswap instruction is only for 32- or 64-bit registers,
so implement the 16-bit swap as a rotate left by 8
11evan added a commit to 11evan/wasmtime that referenced this issue Oct 27, 2022
@11evan
cranelift: Add Bswap instruction (bytecodealliance#1092)
8fee78f 
Adds Bswap to the Cranelift IR. Implements the Bswap instruction
in the x64 and aarch64 codegen backends. Cranelift users can now:
```
builder.ins().bswap(value)
```
to get a native byteswap instruction.

* x64: implements the 32- and 64-bit bswap instruction, following
the pattern set by similar unary instrutions (Neg and Not) - it
only operates on a dst register, but is parameterized with both
a src and dst which are expected to be the same register.

As x64 bswap instruction is only for 32- or 64-bit registers,
the 16-bit swap is implemented as a rotate left by 8.

* aarch64: Bswap gets emitted as aarch64 rev16, rev32,
or rev64 instruction as appropriate.

* s390x: Bswap not implemented

* For completeness, added bswap to the interpreter as well.
@11evan
Copy link
Contributor

11evan commented Oct 27, 2022

Here's an attempt at adding Bswap: #5147

Also tested with a toy program on both x86_64 and aarch64

It's my first contribution to this project, any and all feedback welcome
Who should I tag for reviewing this?

11evan added a commit to 11evan/wasmtime that referenced this issue Oct 28, 2022
@11evan
cranelift: Add Bswap instruction (bytecodealliance#1092)
66833f7 
Adds Bswap to the Cranelift IR. Implements the Bswap instruction
in the x64 and aarch64 codegen backends. Cranelift users can now:
```
builder.ins().bswap(value)
```
to get a native byteswap instruction.

* x64: implements the 32- and 64-bit bswap instruction, following
the pattern set by similar unary instrutions (Neg and Not) - it
only operates on a dst register, but is parameterized with both
a src and dst which are expected to be the same register.

As x64 bswap instruction is only for 32- or 64-bit registers,
the 16-bit swap is implemented as a rotate left by 8.

Updated x64 RexFlags type to support emitting for single-operand
instructions like bswap

* aarch64: Bswap gets emitted as aarch64 rev16, rev32,
or rev64 instruction as appropriate.

* s390x: Bswap was already supported in backend, just had to add
a bit of plumbing

* For completeness, added bswap to the interpreter as well.

* added filetests and runtests for each ISA

* added bswap to fuzzgen, thanks to afonso360 for the code there
11evan added a commit to 11evan/wasmtime that referenced this issue Oct 28, 2022
@11evan
cranelift: Add Bswap instruction (bytecodealliance#1092)
7f2a823 
Adds Bswap to the Cranelift IR. Implements the Bswap instruction
in the x64 and aarch64 codegen backends. Cranelift users can now:
```
builder.ins().bswap(value)
```
to get a native byteswap instruction.

* x64: implements the 32- and 64-bit bswap instruction, following
the pattern set by similar unary instrutions (Neg and Not) - it
only operates on a dst register, but is parameterized with both
a src and dst which are expected to be the same register.

As x64 bswap instruction is only for 32- or 64-bit registers,
the 16-bit swap is implemented as a rotate left by 8.

Updated x64 RexFlags type to support emitting for single-operand
instructions like bswap

* aarch64: Bswap gets emitted as aarch64 rev16, rev32,
or rev64 instruction as appropriate.

* s390x: Bswap was already supported in backend, just had to add
a bit of plumbing

* For completeness, added bswap to the interpreter as well.

* added filetests and runtests for each ISA

* added bswap to fuzzgen, thanks to afonso360 for the code there
11evan added a commit to 11evan/wasmtime that referenced this issue Oct 31, 2022
@11evan
cranelift: Add Bswap instruction (bytecodealliance#1092)
a284a24 
Adds Bswap to the Cranelift IR. Implements the Bswap instruction
in the x64 and aarch64 codegen backends. Cranelift users can now:
```
builder.ins().bswap(value)
```
to get a native byteswap instruction.

* x64: implements the 32- and 64-bit bswap instruction, following
the pattern set by similar unary instrutions (Neg and Not) - it
only operates on a dst register, but is parameterized with both
a src and dst which are expected to be the same register.

As x64 bswap instruction is only for 32- or 64-bit registers,
the 16-bit swap is implemented as a rotate left by 8.

Updated x64 RexFlags type to support emitting for single-operand
instructions like bswap

* aarch64: Bswap gets emitted as aarch64 rev16, rev32,
or rev64 instruction as appropriate.

* s390x: Bswap was already supported in backend, just had to add
a bit of plumbing

* For completeness, added bswap to the interpreter as well.

* added filetests and runtests for each ISA

* added bswap to fuzzgen, thanks to afonso360 for the code there

* 128-bit swaps are not yet implemented, that can be done later
jameysharp pushed a commit that referenced this issue Oct 31, 2022
@11evan
cranelift: Add Bswap instruction (#1092) (#5147)
4ca9e82 
Adds Bswap to the Cranelift IR. Implements the Bswap instruction
in the x64 and aarch64 codegen backends. Cranelift users can now:
```
builder.ins().bswap(value)
```
to get a native byteswap instruction.

* x64: implements the 32- and 64-bit bswap instruction, following
the pattern set by similar unary instrutions (Neg and Not) - it
only operates on a dst register, but is parameterized with both
a src and dst which are expected to be the same register.

As x64 bswap instruction is only for 32- or 64-bit registers,
the 16-bit swap is implemented as a rotate left by 8.

Updated x64 RexFlags type to support emitting for single-operand
instructions like bswap

* aarch64: Bswap gets emitted as aarch64 rev16, rev32,
or rev64 instruction as appropriate.

* s390x: Bswap was already supported in backend, just had to add
a bit of plumbing

* For completeness, added bswap to the interpreter as well.

* added filetests and runtests for each ISA

* added bswap to fuzzgen, thanks to afonso360 for the code there

* 128-bit swaps are not yet implemented, that can be done later
@bjorn3
Copy link
Contributor Author

bjorn3 commented Nov 2, 2022

#5147 mostly implemented this, but bswap.i128 is still missing. cc @jameysharp

@bjorn3
Copy link
Contributor Author

bjorn3 commented Mar 7, 2023

This is now fully implemented.

@bjorn3 bjorn3 closed this as completed Mar 7, 2023
@afonso360 afonso360 mentioned this issue Jul 4, 2023
Merged
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
cranelift:area:clif cranelift:goal:rustc Focus area: Support for compiling Rust! cranelift Issues related to the Cranelift code generator enhancement
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
4 participants
@alexcrichton @cfallin @bjorn3 @11evan