v1.1.0

In this release:

• added integration for ACT .rect files and layout.conf
• flipped cell layouts to put pmos on top and nmos on bottom
• added cell boundary

v1.0.0

Improvements from v0.1.0 to v1.0.0

1. Compound spacing rules
2. Python configuration interface
3. Notch Spacing

Known major issues

1. Virtual pin placement
2. Handling long transistors
3. Optimizing spice parser

v0.1.0

Improvements from v0.0.0 to v0.1.0

1. Support for over-the-cell routing
2. Vias and pins are now shifted to meet horizontal spacing rules
3. Diffusion breaks have been fixed
4. Pin alignment fixes
5. Route lowering fixes

TODO before release

1. Compound spacing rules
2. Python configuration interface
3. Virtual pin placement
4. Notch Spacing
5. Handling long transistors
6. Optimizing spice parser
   
   
   
   

v0.0.0

Cell layouts of standard cells from Skywater 130nm.