Feature: Cortex-A/R speedups #1752
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…ADIv5 encapsulations
… ADIv5 encapsulations
…eaned up in ap_mem_access_setup()
…as done banked or direct, optimising banked access accordingly
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Detailed description
This PR addresses some of the speed concern with Cortex-A/R targets by speeding up (at least for the firmware) accesses that involve instruction launches using the AP banked register interface to improve throughput by reducing ADIv5 protocol overhead for the DBG_ITR, DBG_DTR{T,R}X and DBG_DCSR core debug interface registers.
Tested against the Renesas RZ/A1LU, this delivers at least a 5x speed up in the firmware and 3.75x speed up in BMDA.
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