Remove default max delay; some fixes

ethernet_controller/syn/zedboard/zedboard.tcl

@@ -1,35 +1,20 @@
 
-# Currently this contraint file is highly coupled with Zynq-parrot
+# ** Assign the path of the clk250 source pin to clk250_source_pin before sourcing this tcl **
 
+# Currently this contraint file is highly coupled with Zynq-parrot
 ###################### Clocks ######################
 # clk250 -> clk125
 set inst [get_cells -hier -filter {(ORIG_REF_NAME == tx_clks_generator || REF_NAME == tx_clks_generator)}]
-create_generated_clock -name gtx_clk -source [get_pins {blackparrot_bd_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[1]}] -divide_by 2 [get_pins $inst/gtx_clk_gen/clk_r_o_reg/Q]
+create_generated_clock -name gtx_clk -source [get_pins $clk250_source_pin] -divide_by 2 [get_pins $inst/gtx_clk_gen/clk_r_o_reg/Q]
 # clk250 -> 90-degree shifted clk125 for rgmii TX clk source
-create_generated_clock -name rgmii_tx_clk -source [get_pins {blackparrot_bd_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[1]}] -edges {2 4 6} -edge_shift {0.000 0.000 0.000} [get_ports rgmii_tx_clk_o]
+create_generated_clock -name rgmii_tx_clk -source [get_pins $clk250_source_pin] -edges {2 4 6} -edge_shift {0.000 0.000 0.000} [get_ports rgmii_tx_clk_o]
 # RX clk source (125M)
 create_clock -period 8.000 -name rgmii_rx_clk -waveform {0.000 4.000} [get_ports rgmii_rx_clk_i]
 
-###################### Default max delay ######################
-# Set default max delay between each async clock groups to 0 in order to catch unnoticed paths
-# set_max_delay is used instead of set_clock_groups in order to have safer constraints
-# Async groups:
-# 1. clk_fpga_0(bp_clk)
-# 2. clk_fpga_1 (clk250) (which generates gtx_clk, rgmii_tx_clk)
-# 3. clk_fpga_2 (clk200 for iodelay ctl)
-# 4. rgmii_rx_clk (from Ethernet PHY)
-set_max_delay -from [get_clocks clk_fpga_0] -to [get_clocks {gtx_clk rgmii_tx_clk clk_fpga_1 clk_fpga_2 rgmii_rx_clk}] -datapath_only 0.0
-set_max_delay -from [get_clocks gtx_clk] -to [get_clocks {clk_fpga_0 clk_fpga_2 rgmii_rx_clk}] -datapath_only 0.0
-set_max_delay -from [get_clocks rgmii_tx_clk] -to [get_clocks {clk_fpga_0 clk_fpga_2 rgmii_rx_clk}] -datapath_only 0.0
-set_max_delay -from [get_clocks clk_fpga_1] -to [get_clocks {clk_fpga_0 clk_fpga_2 rgmii_rx_clk}] -datapath_only 0.0
-set_max_delay -from [get_clocks clk_fpga_2] -to [get_clocks {clk_fpga_0 gtx_clk rgmii_tx_clk clk_fpga_1 rgmii_rx_clk}] -datapath_only 0.0
-set_max_delay -from [get_clocks rgmii_rx_clk] -to [get_clocks {clk_fpga_0 gtx_clk rgmii_tx_clk clk_fpga_1 clk_fpga_2}] -datapath_only 0.0
-
 ################# bsg_launch_sync_sync #################
 foreach blss_inst [get_cells -hier -filter {(ORIG_REF_NAME == bsg_launch_sync_sync || REF_NAME == bsg_launch_sync_sync)}] {
   puts "blss_inst: $blss_inst"
-  #foreach launch_reg [get_cells -regexp {$blss_inst/.*/bsg_SYNC_LNCH_r_reg\\[.*]}]
-  foreach launch_reg [get_cells -regexp [format {%s/.*/bsg_SYNC_LNCH_r_reg\\[.*]} $blss_inst]] {
+  foreach launch_reg [get_cells $blss_inst/*/bsg_SYNC_LNCH_r_reg[*]] {
     # ASYNC_REG should have been applied in RTL
     regexp {([\w/.\[\]]+)/[\w]+\[([0-9]+)\]} $launch_reg -> path index