formatting

examples/real_time.rs

@@ -3,8 +3,8 @@ extern crate sdl2;
 
 use rs_nes::cpu::*;
 use rs_nes::input::{Button, Input, InputBase};
-use rs_nes::memory::Memory;
 use rs_nes::memory::nes_memory::NesMemoryImpl;
+use rs_nes::memory::Memory;
 use rs_nes::ppu::{Ppu, PpuImpl};
 use rs_nes::rom::NesRom;
 use sdl2::event::Event;

src/cpu/debugger/cpu_snapshot/mod.rs

@@ -1,8 +1,8 @@
 use base64;
 use cpu::Registers;
 use screen::Screen;
-use serde::{Serialize, Serializer};
 use serde::ser::SerializeStruct;
+use serde::{Serialize, Serializer};
 
 pub enum MemorySnapshot {
     NoChange(u64),         // If no change, just send the hash.

src/cpu/debugger/debugger_command/mod.rs

@@ -1,7 +1,7 @@
 use super::CpuSnapshot;
 use screen::Screen;
-use serde::{Serialize, Serializer};
 use serde::ser::SerializeStruct;
+use serde::{Serialize, Serializer};
 
 // The web socket message sent from the debugger to the client
 pub enum DebuggerCommand<S: Screen + Serialize> {

src/cpu/debugger/http_handlers/mod.rs

@@ -1,15 +1,15 @@
 use super::breakpoint_map::BreakpointMap;
 use cpu::registers::Registers;
-use iron::{headers, status};
-use iron::Handler;
 use iron::modifier::Modifier;
 use iron::prelude::*;
+use iron::Handler;
+use iron::{headers, status};
 use router::{Params, Router};
-use serde::{Serialize, Serializer};
 use serde::ser::SerializeStruct;
+use serde::{Serialize, Serializer};
 use serde_json;
-use std::sync::{Arc, Mutex};
 use std::sync::atomic::{AtomicBool, Ordering};
+use std::sync::{Arc, Mutex};
 use std::thread::Thread;
 
 impl Serialize for Registers {

src/cpu/debugger/mod.rs

@@ -1,24 +1,24 @@
-mod debugger_command;
-mod http_handlers;
 mod breakpoint_map;
 mod cpu_snapshot;
+mod debugger_command;
+mod http_handlers;
 
 use byte_utils::from_lo_hi;
 use chan::{self, Receiver, Sender};
-use cpu::{Cpu, Interrupt};
 use cpu::debugger::breakpoint_map::BreakpointMap;
 use cpu::debugger::cpu_snapshot::{CpuSnapshot, MemorySnapshot};
 use cpu::debugger::debugger_command::{BreakReason, DebuggerCommand};
 use cpu::debugger::http_handlers::*;
+use cpu::{Cpu, Interrupt};
 use input::Input;
 use iron::prelude::*;
 use memory::{Memory, ADDRESSABLE_MEMORY};
 use router::Router;
 use screen::Screen;
 use serde::Serialize;
 use serde_json;
-use std::sync::{Arc, Mutex};
 use std::sync::atomic::{AtomicBool, Ordering};
+use std::sync::{Arc, Mutex};
 use std::thread;
 use websocket::{Message as WsMessage, Server as WsServer};
 

src/cpu/length_and_timing_tests.rs

@@ -15,7 +15,7 @@ use cpu::TestCpu;
 ///     crossing for indirect indexed addressing modes
 ///
 macro_rules! assert_length_and_cycles {
-    ( $ asm : expr , $ expected_len : expr , $ expected_cycles : expr ) => {{
+    ($asm:expr, $expected_len:expr, $expected_cycles:expr) => {{
         let mut cpu = TestCpu::new_test();
         cpu.registers.x = 1;
         cpu.registers.y = 1;
@@ -32,21 +32,25 @@ macro_rules! assert_length_and_cycles {
                 let actual_len = cpu.registers.pc - 0x200;
 
                 if expected_len != actual_len {
-                    panic!("Expected instruction length is {} but it was {}",
-                            expected_len, actual_len)
+                    panic!(
+                        "Expected instruction length is {} but it was {}",
+                        expected_len, actual_len
+                    )
                 }
 
                 if expected_cycles != cpu.cycles {
-                    panic!("Expected number of executed cycles to be {} but it was {}",
-                            expected_cycles, cpu.cycles)
+                    panic!(
+                        "Expected number of executed cycles to be {} but it was {}",
+                        expected_cycles, cpu.cycles
+                    )
                 }
             }
         }
-    }}
+    }};
 }
 
 macro_rules! assert_cycles {
-    ( $ cpu : expr , $ asm : expr , $ expected_cycles : expr ) => {{
+    ($cpu:expr, $asm:expr, $expected_cycles:expr) => {{
         let asm = $asm;
         let mut cpu = $cpu;
         let mut buf = Vec::<u8>::new();
@@ -57,20 +61,22 @@ macro_rules! assert_cycles {
                 let expected_cycles = $expected_cycles;
                 cpu.step();
                 if expected_cycles != cpu.cycles {
-                    panic!("Expected number of executed cycles to be {} but it was {}",
-                            expected_cycles, cpu.cycles)
+                    panic!(
+                        "Expected number of executed cycles to be {} but it was {}",
+                        expected_cycles, cpu.cycles
+                    )
                 }
             }
         }
-    }}
+    }};
 }
 
 /// Similar to the above macro, but for relative instructions. Instead of passing the instruction
 /// length for relative instructions, we pass the expected PC since a branch taken will alter it.
 /// Also, the program counter is set to 0x27f so that can cross the page boundary given a max
 /// offset (relative instruction length + 127 will push PC to 0x300).
 macro_rules! assert_length_and_cycles_relative {
-    ( $ cpu: expr, $ asm : expr , $ expected_len : expr , $ expected_cycles : expr ) => {{
+    ($cpu:expr, $asm:expr, $expected_len:expr, $expected_cycles:expr) => {{
         let mut cpu = $cpu;
         let asm = $asm;
         let mut buf = Vec::<u8>::new();
@@ -85,17 +91,21 @@ macro_rules! assert_length_and_cycles_relative {
                 let actual_len = cpu.registers.pc - 0x27f;
 
                 if expected_len != actual_len {
-                    panic!("Expected instruction length is {} but it was {}",
-                            expected_len, actual_len)
+                    panic!(
+                        "Expected instruction length is {} but it was {}",
+                        expected_len, actual_len
+                    )
                 }
 
                 if expected_cycles != cpu.cycles {
-                    panic!("Expected number of executed cycles to be {} but it was {}",
-                            expected_cycles, cpu.cycles)
+                    panic!(
+                        "Expected number of executed cycles to be {} but it was {}",
+                        expected_cycles, cpu.cycles
+                    )
                 }
             }
         }
-    }}
+    }};
 }
 
 #[test]

src/cpu/mod.rs

@@ -10,8 +10,8 @@ mod length_and_timing_tests;
 #[cfg(feature = "debugger")]
 pub mod debugger;
 
-mod registers;
 mod opcodes;
+mod registers;
 
 use byte_utils::{from_lo_hi, lo_hi, wrapping_dec, wrapping_inc};
 use cpu::registers::Registers;

src/cpu/opcodes/am_test_utils.rs

@@ -1,5 +1,5 @@
-use cpu::{TestCpu, TestMemory};
 use cpu::opcodes::AddressingMode;
+use cpu::{TestCpu, TestMemory};
 use input::NoInput;
 use screen::NoScreen;
 use std::cell::Cell;

src/cpu/opcodes/arithmetic_instr_spec_tests.rs

@@ -1,5 +1,5 @@
-use cpu::*;
 use cpu::opcodes::*;
+use cpu::*;
 
 /// ## Sign and zero flag tests
 ///

src/cpu/opcodes/bitwise_and_shift_instr_spec_tests.rs

@@ -1,5 +1,5 @@
-use cpu::*;
 use cpu::opcodes::*;
+use cpu::*;
 
 fn asl(cpu: &mut TestCpu, val: u8) -> (u8, bool) {
     Asl::execute(cpu, val);

src/cpu/opcodes/branch_spec_tests.rs

@@ -1,5 +1,5 @@
-use cpu::*;
 use cpu::opcodes::*;
+use cpu::*;
 
 #[test]
 fn bpl_not_crossing_page_boundary_positive_offset() {

src/cpu/opcodes/compare_spec_tests.rs

@@ -1,5 +1,5 @@
-use cpu::*;
 use cpu::opcodes::*;
+use cpu::*;
 
 #[test]
 fn cmp_equal_flag_check() {

src/cpu/opcodes/flag_instr_spec_tests.rs

@@ -1,5 +1,5 @@
-use cpu::*;
 use cpu::opcodes::*;
+use cpu::*;
 
 #[test]
 fn sei() {

src/cpu/opcodes/inc_dec_spec_tests.rs

@@ -1,6 +1,6 @@
-use cpu::*;
-use cpu::opcodes::*;
 use cpu::opcodes::am_test_utils::*;
+use cpu::opcodes::*;
+use cpu::*;
 
 #[test]
 fn dec_test1() {

src/cpu/opcodes/jump_and_returns_instr_spec_tests.rs

@@ -1,7 +1,7 @@
 // TODO: RTI, BRK tests
 
-use cpu::*;
 use cpu::opcodes::*;
+use cpu::*;
 
 #[test]
 fn jmp() {

src/cpu/opcodes/loads_and_stores_spec_tests.rs

@@ -1,6 +1,6 @@
-use cpu::*;
-use cpu::opcodes::*;
 use cpu::opcodes::am_test_utils::*;
+use cpu::opcodes::*;
+use cpu::*;
 
 #[test]
 fn lda_value_set() {

src/cpu/opcodes/reg_transfer_spec_tests.rs

@@ -1,7 +1,7 @@
 // TODO: Tests to assert status flags
 
-use cpu::*;
 use cpu::opcodes::*;
+use cpu::*;
 
 #[test]
 fn tax() {

src/lib.rs

@@ -48,11 +48,11 @@ extern crate asm6502;
 #[cfg(test)]
 extern crate rand;
 
-pub mod rom;
-pub mod memory;
+mod apu;
+mod byte_utils;
 pub mod cpu;
+pub mod input;
+pub mod memory;
 pub mod ppu;
+pub mod rom;
 pub mod screen;
-pub mod input;
-mod apu;
-mod byte_utils;

src/memory/nes_memory/mod.rs

@@ -14,14 +14,12 @@ use std::io::Write;
 use std::rc::Rc;
 
 macro_rules! dma_tick {
-    ( $mem : expr ) => {
-        {
-            let tick_action = $mem.tick();
-            if tick_action != Interrupt::None {
-                panic!("unimplemented: nmi during dma")
-            }
+    ($mem:expr) => {{
+        let tick_action = $mem.tick();
+        if tick_action != Interrupt::None {
+            panic!("unimplemented: nmi during dma")
         }
-    };
+    }};
 }
 
 pub type NesMemoryImpl = NesMemoryBase<PpuImpl, ApuBase, InputBase>;