Better i2 s clocking redux #1419
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32 bits of I2S data completely fill the frame instead of it all being in the L clock phase. That lets us run the bit clock at half the rate, for better compatibility with slower shift registers like the HC logic family which is 5x slower than AHCT. It also lets us increase the frame rate to 1 MHz (requirese fast shift registers) for a pulse rate up to 500K pulses/sec. The rate is configurable by setting $/i2so/min_pulse_us to 1, 2 or 4 (default 2).
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Trying to fix merge conflict