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[Mellanox]Adding SKU Mellanox-SN4700-O32 and Mellanox-SN4700-V64 (so…
…nic-net#19681) A new SKUs for MSN4700 Platform: Mellanox-SN4700-O32 and Mellanox-SN4700-V64 Requirements for Mellanox-SN4700-O32: 8 x 400Gbps uplink to T2 switch (O13 to O20) 24 x 400Gbps downlinks to T0 switch (O1-O12, O21-O32) Breakout mode No breakout mode. All ports working in 400Gb mode. . FEC mode: RS Type of transceiver: 400Gb Optical. warm boot should be supported “No for T1 role” VxLAN source port range set N/A Static Policy Based Hashing supported N/A Cable length “T0-T1 40m default, 300m max; T1-T2 2000m” Tradition buffer model is must “Yes” Shared headroom should be supported “Yes” Over-subscription ratio: “2”. Requirements for Mellanox-SN4700-V64 16 x 200Gbps uplink to T1 switch (V-25&V26 to V-39&40) 48 x 200Gbps downlinks to servers (Left panel downlink ports: V-1&2 to V-23&24; Right panel downlink ports: V-41&42 to V-63&64) Breakout mode split from 400Gbps ports (2x200) FEC mode: RS Type of transceiver: 200Gb AOC between T0 and T1; 200Gb DAC between T0 and host. warm boot should be supported “Yes for T0 role” VxLAN source port range set N/A Static Policy Based Hashing supported N/A Cable length “T0-T1 40m default, 300m max, T0-Server 5m” Tradition buffer model is must “Yes” Shared headroom should be supported “Yes” Over-subscription ratio: “2”. Additional Details: QoS configs for Mellanox-SN4700-V64 updated in order to fulfill Dual-ToR buffer (+DSCP remapping) requirements Support for independent module added for both SKUs, so Auto-negotiation changed to NO Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/buffers.json.j2
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| {# | ||
| Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. | ||
| Apache-2.0 | ||
| Licensed under the Apache License, Version 2.0 (the "License"); | ||
| you may not use this file except in compliance with the License. | ||
| You may obtain a copy of the License at | ||
| http://www.apache.org/licenses/LICENSE-2.0 | ||
| Unless required by applicable law or agreed to in writing, software | ||
| distributed under the License is distributed on an "AS IS" BASIS, | ||
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| See the License for the specific language governing permissions and | ||
| limitations under the License. | ||
| #} | ||
| {%- set default_topo = 't1' %} | ||
| {%- include 'buffers_config.j2' %} |
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/buffers_defaults_objects.j2
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| ../../x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/buffers_defaults_objects.j2 |
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/buffers_defaults_t0.j2
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| {# | ||
| Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. | ||
| Apache-2.0 | ||
| Licensed under the Apache License, Version 2.0 (the "License"); | ||
| you may not use this file except in compliance with the License. | ||
| You may obtain a copy of the License at | ||
| http://www.apache.org/licenses/LICENSE-2.0 | ||
| Unless required by applicable law or agreed to in writing, software | ||
| distributed under the License is distributed on an "AS IS" BASIS, | ||
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| See the License for the specific language governing permissions and | ||
| limitations under the License. | ||
| #} | ||
| {% set default_cable = '5m' %} | ||
| {% set ingress_lossless_pool_size = '51806208' %} | ||
| {% set ingress_lossless_pool_xoff = '3407872' %} | ||
| {% set egress_lossless_pool_size = '60817392' %} | ||
| {% set egress_lossy_pool_size = '51806208' %} | ||
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| {% import 'buffers_defaults_objects.j2' as defs with context %} | ||
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| {%- macro generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) %} | ||
| {{ defs.generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) }} | ||
| {%- endmacro %} | ||
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| {%- macro generate_profile_lists_with_inactive_ports(port_names_active, port_names_inactive) %} | ||
| {{ defs.generate_profile_lists(port_names_active, port_names_inactive) }} | ||
| {%- endmacro %} | ||
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| {%- macro generate_queue_buffers_with_inactive_ports(port_names_active, port_names_inactive) %} | ||
| {{ defs.generate_queue_buffers(port_names_active, port_names_inactive) }} | ||
| {%- endmacro %} | ||
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| {%- macro generate_pg_profiles_with_inactive_ports(port_names_active, port_names_inactive) %} | ||
| {{ defs.generate_pg_profiles(port_names_active, port_names_inactive) }} | ||
| {%- endmacro %} |
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/buffers_defaults_t1.j2
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| {# | ||
| Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. | ||
| Apache-2.0 | ||
| Licensed under the Apache License, Version 2.0 (the "License"); | ||
| you may not use this file except in compliance with the License. | ||
| You may obtain a copy of the License at | ||
| http://www.apache.org/licenses/LICENSE-2.0 | ||
| Unless required by applicable law or agreed to in writing, software | ||
| distributed under the License is distributed on an "AS IS" BASIS, | ||
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| See the License for the specific language governing permissions and | ||
| limitations under the License. | ||
| #} | ||
| {% set default_cable = '40m' %} | ||
| {% set ingress_lossless_pool_size = '45531136' %} | ||
| {% set ingress_lossless_pool_xoff = '9682944' %} | ||
| {% set egress_lossless_pool_size = '60817392' %} | ||
| {% set egress_lossy_pool_size = '45531136' %} | ||
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| {% import 'buffers_defaults_objects.j2' as defs with context %} | ||
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| {%- macro generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) %} | ||
| {{ defs.generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) }} | ||
| {%- endmacro %} | ||
|
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| {%- macro generate_profile_lists_with_inactive_ports(port_names_active, port_names_inactive) %} | ||
| {{ defs.generate_profile_lists(port_names_active, port_names_inactive) }} | ||
| {%- endmacro %} | ||
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| {%- macro generate_queue_buffers_with_inactive_ports(port_names_active, port_names_inactive) %} | ||
| {{ defs.generate_queue_buffers(port_names_active, port_names_inactive) }} | ||
| {%- endmacro %} | ||
|
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| {%- macro generate_pg_profiles_with_inactive_ports(port_names_active, port_names_inactive) %} | ||
| {{ defs.generate_pg_profiles(port_names_active, port_names_inactive) }} | ||
| {%- endmacro %} |
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/buffers_dynamic.json.j2
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| {# | ||
| Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. | ||
| Apache-2.0 | ||
| Licensed under the Apache License, Version 2.0 (the "License"); | ||
| you may not use this file except in compliance with the License. | ||
| You may obtain a copy of the License at | ||
| http://www.apache.org/licenses/LICENSE-2.0 | ||
| Unless required by applicable law or agreed to in writing, software | ||
| distributed under the License is distributed on an "AS IS" BASIS, | ||
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| See the License for the specific language governing permissions and | ||
| limitations under the License. | ||
| #} | ||
| {%- set default_topo = 't1' %} | ||
| {%- set dynamic_mode = 'true' %} | ||
| {%- include 'buffers_config.j2' %} |
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/hwsku.json
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| { | ||
| "interfaces": { | ||
| "Ethernet0": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet8": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet16": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet24": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet32": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet40": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet48": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet56": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet64": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet72": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet80": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet88": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet96": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet104": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet112": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet120": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet128": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet136": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet144": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet152": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet160": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet168": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet176": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet184": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet192": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet200": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet208": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet216": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet224": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet232": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet240": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| }, | ||
| "Ethernet248": { | ||
| "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]", | ||
| "autoneg": "off" | ||
| } | ||
| } | ||
| } |
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/media_settings.json
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| ../Mellanox-SN4700-O8C48/media_settings.json |
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/optics_si_settings.json
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| ../Mellanox-SN4700-O8C48/optics_si_settings.json |
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/pg_profile_lookup.ini
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| ../../x86_64-nvidia_sn4280-r0/ACS-SN4280/pg_profile_lookup.ini |
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/pmon_daemon_control.json
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| { | ||
| "skip_ledd": true, | ||
| "skip_fancontrol": true, | ||
| "skip_xcvrd_cmis_mgr": false | ||
| } | ||
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/port_config.ini
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| ../ACS-MSN4700/port_config.ini |
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/qos.json.j2
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| ../../x86_64-mlnx_msn2700-r0/ACS-MSN2700/qos.json.j2 |
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device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/sai.profile
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| SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4700_32x400g.xml | ||
| SAI_INDEPENDENT_MODULE_MODE=1 |
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