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Iso/jau/stih418 b2264 v6.2 #1

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Iso/jau/stih418 b2264 v6.2 #1

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adbde61
ARM: kernel: add support for cpu cache information
sudeep-holla Feb 23, 2015
a5ebf6c
ARM: kernel: cacheinfo: Get rid of DEFINE_SMP_CALL_CACHE_FUNCTION()
waby38b Sep 20, 2021
c7801b6
cpufreq: sti: align to mainline requierement
waby38b Sep 29, 2021
c099191
ARM: dts: sti: enable USB3 LPM on dwc3 controleur
waby38b Sep 2, 2022
8a67b20
usb: dwc3: st: Switch from CONFIG_PM_SLEEP guards to pm_sleep_ptr()
waby38b Jan 9, 2023
163a194
mmc: sdhci-st: Switch from CONFIG_PM_SLEEP guards to pm_sleep_ptr()
waby38b Jan 9, 2023
f1895b1
mtd: st_spi_fsm: Switch from CONFIG_PM_SLEEP guards to pm_sleep_ptr()
waby38b Jan 9, 2023
ba21416
ahci: st: Switch from CONFIG_PM_SLEEP guards to pm_sleep_ptr()
waby38b Jan 9, 2023
5d05fea
net: stmmac: sti: Switch from CONFIG_PM_SLEEP guards to pm_sleep_ptr()
waby38b Jan 9, 2023
e10444f
serial: st-asc: Switch from CONFIG_PM_SLEEP guards to pm_sleep_ptr()
waby38b Jan 9, 2023
3f92db6
thermal: sti: Switch from CONFIG_PM_SLEEP guards to pm_sleep_ptr()
waby38b Mar 1, 2023
22fac29
thermal: sti: remove dead entry
waby38b Mar 1, 2023
f496c95
dts: arm: stih418: add alias for CPUs
waby38b Mar 1, 2023
74781cb
dts: arm: stih418: add new alias for thermal entry
waby38b Mar 1, 2023
61449b3
dts: arm: stih418: add thermal-zones support
waby38b Mar 1, 2023
aa5b7e9
thermal: sti: switch to thermal_of_zone to handle thermal-zones
waby38b Mar 1, 2023
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1 change: 0 additions & 1 deletion Documentation/devicetree/bindings/thermal/st-thermal.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -28,5 +28,4 @@ Example:
clock-names = "thermal";
clocks = <&CLK_SYSIN>;
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
st,passive_cooling_temp = <110>;
};
9 changes: 7 additions & 2 deletions arch/arm/boot/dts/stih407-family.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
Expand All @@ -52,8 +52,9 @@
clock-latency = <100000>;
cpu0-supply = <&pwm_regulator>;
st,syscfg = <&syscfg_core 0x8e0>;
#cooling-cells = <2>;
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
Expand All @@ -66,6 +67,7 @@
1200000 0
800000 0
500000 0>;
#cooling-cells = <2>;
};
};

Expand Down Expand Up @@ -734,6 +736,9 @@
phys = <&usb2_picophy0>,
<&phy_port2 PHY_TYPE_USB3>;
snps,dis_u3_susphy_quirk;
snps,usb3_lpm_capable;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
};
};

Expand Down
4 changes: 0 additions & 4 deletions arch/arm/boot/dts/stih418-b2264.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -62,10 +62,6 @@
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <784000>;
};
opp04 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <784000>;
};
};

aliases {
Expand Down
42 changes: 39 additions & 3 deletions arch/arm/boot/dts/stih418.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -6,23 +6,26 @@
#include "stih418-clock.dtsi"
#include "stih407-family.dtsi"
#include "stih410-pinctrl.dtsi"
#include <dt-bindings/thermal/thermal.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
/* u-boot puts hpen in SBC dmem at 0xa4 offset */
cpu-release-addr = <0x94100A4>;
#cooling-cells = <2>;
};
cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
/* u-boot puts hpen in SBC dmem at 0xa4 offset */
cpu-release-addr = <0x94100A4>;
#cooling-cells = <2>;
};
};

Expand All @@ -44,6 +47,38 @@
reset-names = "global", "port";
};

thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <250>; /* 250ms */
polling-delay = <1000>; /* 1000ms */

thermal-sensors = <&thermal>;

trips {
cpu_crit: cpu-crit {
temperature = <95000>; /* 95C */
hysteresis = <2000>;
type = "critical";
};
cpu_alert: cpu-alert {
temperature = <85000>; /* 85C */
hysteresis = <2000>;
type = "passive";
};
};

cooling-maps {
map {
trip = <&cpu_alert>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};

soc {
rng11: rng@8a8a000 {
status = "disabled";
Expand Down Expand Up @@ -107,12 +142,13 @@
assigned-clock-rates = <200000000>;
};

thermal@91a0000 {
thermal: thermal@91a0000 {
compatible = "st,stih407-thermal";
reg = <0x91a0000 0x28>;
clock-names = "thermal";
clocks = <&clk_sysin>;
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
#thermal-sensor-cells = <0>;
};
};
};
1 change: 1 addition & 0 deletions arch/arm/kernel/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,7 @@ obj-y += entry-v7m.o v7m.o
else
obj-y += entry-armv.o
endif
obj-$(CONFIG_CPU_HAS_CACHE) += cacheinfo.o

obj-$(CONFIG_MMU) += bugs.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
Expand Down
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