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32 Open 46 Closed
32 Open 46 Closed
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Issues list

axi_bram has fixed width because of 1rwm address logic
#78 opened Nov 8, 2021 by armleo
RISC-V Timer can be optimized enhancement New feature or request good first issue Good for newcomers help wanted Extra attention is needed
#77 opened Aug 21, 2021 by armleo 0.0.2
Exclusive monitor implementation is wrong. More optimal solution is possible. bug Something isn't working good first issue Good for newcomers
#74 opened Jul 31, 2021 by armleo 0.0.2
4
Add more tests testing limits of TLB (including victim_way checking) bug Something isn't working good first issue Good for newcomers
#72 opened Jul 24, 2021 by armleo 0.0.2
Implement CSR remaining commands
#71 opened Jul 22, 2021 by armleo 0.0.2
Fix Cache implementation
#70 opened Jul 22, 2021 by armleo 0.0.2
1
Verilator Lints: Remove global lint off-s
#69 opened Jul 22, 2021 by armleo 0.0.2
Interrupt after branch taken contains incorrect PC
#68 opened Jul 21, 2021 by armleo 0.0.2
Skywater130 tapeout
#66 opened Jul 19, 2021 by armleo 0.0.2
New Pipelined Cache architecture with 3 cycle deep pipeline
#65 opened Jul 19, 2021 by armleo 0.0.2
1
AXI Register Slice
#62 opened Jul 13, 2021 by armleo 0.0.2
More CSR Tests good first issue Good for newcomers
#60 opened Jul 13, 2021 by armleo 0.0.2
@armleo
Make CLINT/PLIC CXXRTL models and run them under qemu or spike
#59 opened Jul 13, 2021 by armleo 0.0.2
1
More Cache tests
#58 opened Jul 10, 2021 by armleo 0.0.2
@armleo
Some peripherals don't properly return IDs, test this properly because b_expect does not check id value
#55 opened Jun 30, 2021 by armleo 0.0.2
@armleo
Implement ATOMIC Read-Modify-Write Instructions
#53 opened Jun 25, 2021 by armleo 0.0.2
@armleo
Implement simple UART8250 good first issue Good for newcomers
#52 opened Jun 25, 2021 by armleo 0.0.2
@armleo
Implement CLINT/PLIC enhancement New feature or request good first issue Good for newcomers
#51 opened Jun 25, 2021 by armleo 0.0.2
@armleo
4
Cache: Write should not invalidate cache data, instead just write it to storage enhancement New feature or request good first issue Good for newcomers
#50 opened Jun 25, 2021 by armleo
Add formal verification
#47 opened Jun 23, 2021 by armleo
9
AXI Arbiter
#46 opened Jun 23, 2021 by armleo 0.0.2
@armleo
chip2chip
#44 opened Jun 19, 2021 by armleo 0.0.2
@armleo
Proper verif-isa-tests environment
#40 opened Jun 16, 2021 by armleo 0.0.2
@armleo
New Decode + Pipeline
#32 opened May 27, 2021 by armleo 0.0.2
@armleo
Write through buffer good first issue Good for newcomers long term
#30 opened May 27, 2021 by armleo
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