rockchip64: rk3399 fix pcie being stuck at 1x width after a warm phy reset

[walmis]

Description

This patch fixes an issue in the Rockchip PCIe PHY driver where, after a warm restart of the rockchip_pcie_phy module, PCIe lanes other than lane 0 could remain stuck in the PHY_LANE_IDLE_OFF state. This resulted in the PCIe link being restricted to x1 mode, even in configurations designed to use multiple lanes.

The patch moves the regmap_write block, which disables the PHY_LANE_IDLE_OFF state, to a position before the if (rk_phy->pwr_cnt++) goto err_out; condition. This ensures that all lanes are properly re-enabled during the rockchip_pcie_phy_power_on function, which is called for each pcie lane, fixing the multi-lane handling issue.

GitHub issue reference:
#6655

Documentation summary for feature / change

• Short description: Fix multi-lane PCIe initialization issue after warm restart.
• Summary: Ensures proper re-enabling of all PCIe lanes in rockchip_pcie_phy_power_on by addressing a warm restart issue that left non-zero lanes in the PHY_LANE_IDLE_OFF state. This fixes scenarios where the PCIe link was incorrectly limited to x1 mode.
• Example of usage: Changes are internal to the driver. End users can verify functionality by ensuring PCIe links initialize correctly with the expected lane count after warm restarts.

How Has This Been Tested?

This patch has been tested with the following:

• Multi-lane PCIe configurations to verify proper initialization after a warm restart.
• Single-lane PCIe configurations to confirm no regressions were introduced.
• Regression tests for other PHY-related operations.

Checklist:

• My code follows the style guidelines of this project.
• I have performed a self-review of my own code.
• I have commented my code, particularly in hard-to-understand areas.
• My changes generate no new warnings.
• Any dependent changes have been merged and published in downstream modules.