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Updates to allow loopback tests of CPLD programming status
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@dgastler
dgastler committed May 11, 2023
1 parent d1ef372 commit 0e7b842
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Showing 3 changed files with 30 additions and 17 deletions.
20 changes: 14 additions & 6 deletions program.py
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@


def parse_cli():
"""Parse command line arguments and make some checks on the arguments."""
"""Parse command line aruiguments and make some checks on the arguments."""
parser = argparse.ArgumentParser()

parser.add_argument('--VIVADO_SOURCE', default="/work/Xilinx/Vivado/2020.2/settings64.sh", help='path to vivado sourcing script')
Expand All @@ -40,7 +40,8 @@ def parse_cli():
parser.add_argument('--xvc_ip' , default=None, help='IP of xvc server for CPLD')
parser.add_argument('--xvc_port', default=2545, help='port of xvc server for CPLD')
parser.add_argument('--jed_file', default=None, help='jed file to program the CPLD')

parser.add_argument('--gui',default=False)

args = parser.parse_args()

return args
Expand Down Expand Up @@ -70,7 +71,10 @@ def main():
xvc_port=args.xvc_port)
)
outFile.close()
xvc_cmd="source "+args.VIVADO_SOURCE+";vivado -mode tcl -source "+outFileName1
if not args.gui:
xvc_cmd="source "+args.VIVADO_SOURCE+";vivado -mode tcl -source "+outFileName1
else:
xvc_cmd="source "+args.VIVADO_SOURCE+";vivado -mode gui -source "+outFileName1
print(xvc_cmd)
xvc_proc = subprocess.Popen(xvc_cmd,
shell=True,
Expand All @@ -81,7 +85,7 @@ def main():


#wait for xvc to be loaded
while(True):
while(not args.gui):
outs = xvc_proc.stdout.readline()
if outs == None:
continue
Expand All @@ -91,7 +95,8 @@ def main():
if outs.find('xvc running') > -1:
break



time.sleep(30)
#############################################################################
#Prog
#############################################################################
Expand All @@ -103,7 +108,10 @@ def main():
))
outFile.close()

ise_cmd="source "+args.ISE_SOURCE+"; impact -batch "+outFileName2
if not args.gui:
ise_cmd="source "+args.ISE_SOURCE+"; impact -batch "+outFileName2
else:
ise_cmd="source "+args.ISE_SOURCE+"; impact"
print(ise_cmd)
ise_proc = subprocess.Popen(ise_cmd,shell=True,preexec_fn=os.setsid)

Expand Down
14 changes: 8 additions & 6 deletions src/top.ucf
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Original file line number Diff line number Diff line change
Expand Up @@ -17,8 +17,10 @@ NET "Master_Cable_nRST" LOC=P32 | IOSTANDARD="LVCMOS33";

NET "Master_IPMC_TCK" LOC=P22 | IOSTANDARD="LVCMOS33";
NET "Master_IPMC_TMS" LOC=P14 | IOSTANDARD="LVCMOS33";
NET "Master_IPMC_TDI" LOC=P15 | IOSTANDARD="LVCMOS33";
NET "Master_IPMC_TDO" LOC=P16 | IOSTANDARD="LVCMOS33";
#NET "Master_IPMC_TDI" LOC=P15 | IOSTANDARD="LVCMOS33";
#NET "Master_IPMC_TDO" LOC=P16 | IOSTANDARD="LVCMOS33";
NET "Master_IPMC_TDO" LOC=P15 | IOSTANDARD="LVCMOS33";
NET "Master_IPMC_TDI" LOC=P16 | IOSTANDARD="LVCMOS33";
NET "Master_IPMC_nRST" LOC=P17 | IOSTANDARD="LVCMOS33";

NET "Master_Zynq_TCK<0>" LOC=P13 | IOSTANDARD="LVCMOS33";
Expand Down Expand Up @@ -71,10 +73,10 @@ NET "IPMC_UART<1>" LOC=P19 | IOSTANDARD="LVCMOS33" | PULLDOWN;
NET "IPMC_UART<2>" LOC=P41 | IOSTANDARD="LVCMOS33" | PULLDOWN;
NET "IPMC_UART<3>" LOC=P42 | IOSTANDARD="LVCMOS33" | PULLDOWN;

NET "Zynq_GPIO<0>" LOC=P27 | IOSTANDARD="LVCMOS33" | PULLDOWN;
NET "Zynq_GPIO<1>" LOC=P34 | IOSTANDARD="LVCMOS33" | PULLDOWN;
NET "Zynq_GPIO<2>" LOC=P1 | IOSTANDARD="LVCMOS33" | PULLDOWN;
NET "Zynq_GPIO<3>" LOC=P99 | IOSTANDARD="LVCMOS33" | PULLDOWN;
NET "Zynq_in<0>" LOC=P27 | IOSTANDARD="LVCMOS33" | PULLDOWN;
NET "Zynq_in<1>" LOC=P34 | IOSTANDARD="LVCMOS33" | PULLDOWN;
NET "Zynq_in<2>" LOC=P1 | IOSTANDARD="LVCMOS33" | PULLDOWN;
NET "Zynq_out<0>" LOC=P99 | IOSTANDARD="LVCMOS33" | PULLDOWN;

NET "Mezz1_GPIO<0>" LOC=P97 | IOSTANDARD="LVCMOS33" | PULLDOWN;
NET "Mezz1_GPIO<1>" LOC=P94 | IOSTANDARD="LVCMOS33" | PULLDOWN;
Expand Down
13 changes: 8 additions & 5 deletions src/top.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,8 @@ entity top is
cable_present_n : in std_logic;
GPIO : in std_logic_vector(3 downto 0);
IPMC_UART : in std_logic_vector(3 downto 0);
Zynq_GPIO : in std_logic_vector(3 downto 0);
Zynq_in : in std_logic_vector(2 downto 0);
Zynq_out : out std_logic_vector(0 downto 0);
Mezz1_GPIO : in std_logic_vector(1 downto 0);
Mezz2_GPIO : in std_logic_vector(1 downto 0)
);
Expand All @@ -55,8 +56,9 @@ architecture behavioral of top is
begin -- architecture behavioral

IPMC_Cable_switch: process (cable_present_n,
Master_Cable_TCK, Master_Cable_TMS,Master_Cable_TDI,
Master_IPMC_TCK, Master_IPMC_TMS,Master_IPMC_TDI
Master_Cable_TCK, Master_Cable_TMS,Master_Cable_TDI, Master_Cable_nRST,
Master_IPMC_TCK, Master_IPMC_TMS,Master_IPMC_TDI,Master_IPMC_nRST,
local_Board_TDO
) is
begin -- process IPMC_Cable_switch
if cable_present_n = '0' then
Expand All @@ -82,7 +84,8 @@ architecture behavioral of top is

switch: process (sel,mezz_en,zynq_pwr_ngood,
Master_Zynq_TCK,Master_Zynq_TMS,Master_Zynq_TDI,Master_Zynq_nRST,
local_Board_TCK,local_Board_TMS,local_Board_TDI,local_Board_nRST) is
local_Board_TCK,local_Board_TMS,local_Board_TDI,local_Board_nRST,
Slave_Mezz_TDO,Slave_Zynq_TDO) is
variable mezzSel : integer range 0 to 1;
begin -- process switch
mezzSel := to_integer(unsigned(sel(0 downto 0)));
Expand Down Expand Up @@ -168,6 +171,6 @@ architecture behavioral of top is
end case;
end process switch;

Zynq_out(0) <= Zynq_in(2);


end architecture behavioral;

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