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[CUDA] Support multiple TIR-level dynamic shared memory allocations #8571
Commits on Jul 27, 2021
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add builtin for reinterprete load/store
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remove buitlin since Load/Store node already support reinterpret
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Add Load/Store visitor implementation
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Remove all attr::storage_scope usage
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Revert "Remove all attr::storage_scope usage"
This reverts commit ce62d9e.
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Commits on Jul 28, 2021
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drop multi-lane dtype allocation support, vectorized store working
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lint fix, do not run merging when number of alloc is 1
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Commits on Jul 29, 2021
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Update src/tir/transforms/merge_dynamic_shared_memory_allocations.cc
Co-authored-by: Siyuan Feng <Hzfengsy@sjtu.edu.cn>
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Update src/tir/transforms/merge_dynamic_shared_memory_allocations.cc
Co-authored-by: Siyuan Feng <Hzfengsy@sjtu.edu.cn>
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move test cases into dedicated file
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verify new transform pass output
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Commits on Jul 30, 2021
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