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[VTA][Chisel] run all unittests by default #3766

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merged 3 commits into from
Aug 13, 2019
Merged

[VTA][Chisel] run all unittests by default #3766

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60fb7b0
[VTA][Chisel] run all unittests by default
vegaluisjose Aug 13, 2019
adc72fa
better naming
vegaluisjose Aug 13, 2019
fbd2ac8
add generated unittest folder to clean rule
vegaluisjose Aug 13, 2019
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8 changes: 4 additions & 4 deletions vta/hardware/chisel/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -38,13 +38,13 @@ TOP_TEST = Test
BUILD_NAME = build
USE_TRACE = 0
VTA_LIBNAME = libvta_hw
UNITTEST_NAME = all

config_test = $(TOP_TEST)$(CONFIG)
vta_dir = $(abspath ../../)
tvm_dir = $(abspath ../../../)
verilator_build_dir = $(vta_dir)/$(BUILD_NAME)/verilator
chisel_build_dir = $(vta_dir)/$(BUILD_NAME)/chisel
test_name = mvm

verilator_opt = --cc
verilator_opt += +define+RANDOMIZE_GARBAGE_ASSIGN
Expand Down Expand Up @@ -112,11 +112,11 @@ verilog_test: $(chisel_build_dir)/$(TOP_TEST).$(CONFIG).v
$(chisel_build_dir)/$(TOP_TEST).$(CONFIG).v:
sbt 'runMain vta.$(config_test) --target-dir $(chisel_build_dir) --top-name $(TOP_TEST).$(CONFIG)'

test:
sbt 'test:runMain unittest.Launcher $(test_name)'
unittest:
sbt 'test:runMain unittest.Launcher $(UNITTEST_NAME)'

clean:
-rm -rf target project/target project/project
-rm -rf target project/target project/project test_run_dir

cleanall:
-rm -rf $(vta_dir)/$(BUILD_NAME)