[Target] Replace IsaAnalyzer with Target Features (#12322)

This is clean up to use the new `target.features` instead of `IsaAnalyzer`.

python/tvm/relay/op/strategy/arm_cpu.py

@@ -24,7 +24,6 @@
 
 from ....auto_scheduler import is_auto_scheduler_enabled
 from ....meta_schedule import is_meta_schedule_enabled
-from ....target import arm_isa
 from ....topi.generic import conv2d as conv2d_generic
 from .. import op as _op
 from .generic import *
@@ -57,15 +56,14 @@ def schedule_concatenate_arm_cpu(_, outs, target):
 def schedule_pool_arm_cpu(attrs, outs, target):
     """schedule pooling ops arm cpu"""
     layout = attrs.layout
-    isa = arm_isa.IsaAnalyzer(target)
     avg_pool = isinstance(attrs, relay.op.op_attrs.AvgPool2DAttrs)
     with target:
         if (
             avg_pool
-            and isa.has_dsp_support
+            and target.features.has_dsp
             and layout in ("NCW", "NCHW")
             or not avg_pool
-            and isa.has_dsp_support
+            and target.features.has_dsp
             and layout in ("NWC", "NHWC")
         ):
             return topi.arm_cpu.schedule_pool(outs, layout)
@@ -87,8 +85,6 @@ def conv2d_strategy_arm_cpu(attrs, inputs, out_type, target):
     if dilation_h < 1 or dilation_w < 1:
         raise ValueError("dilation should be positive value")
 
-    isa = arm_isa.IsaAnalyzer(target)
-
     if groups == 1:
         if layout == "NCHW":
             if kernel_layout == "OIHW":
@@ -163,7 +159,7 @@ def conv2d_strategy_arm_cpu(attrs, inputs, out_type, target):
                 name="conv2d_hwcn.generic",
             )
         elif layout == "NHWC":
-            if isa.has_dsp_support and kernel_layout == "HWOI":
+            if target.features.has_dsp and kernel_layout == "HWOI":
                 strategy.add_implementation(
                     wrap_compute_conv2d(topi.arm_cpu.conv2d_nhwc_dsp),
                     wrap_topi_schedule(topi.arm_cpu.schedule_conv2d_nhwc_dsp),
@@ -473,10 +469,9 @@ def schedule_bitserial_dense_arm_cpu(attrs, inputs, out_type, target):
 def schedule_dense_arm_cpu(attrs, inputs, out_type, target):
     """dense arm cpu strategy"""
     strategy = _op.OpStrategy()
-    isa = arm_isa.IsaAnalyzer(target)
     data, _ = inputs
 
-    if isa.has_dsp_support and data.dtype in ["int8", "int16"]:
+    if target.features.has_dsp and data.dtype in ["int8", "int16"]:
         strategy.add_implementation(
             wrap_compute_dense(topi.arm_cpu.dense_dsp),
             wrap_topi_schedule(topi.arm_cpu.schedule_dense_dsp),
@@ -506,10 +501,8 @@ def conv1d_strategy_arm_cpu(attrs, inputs, out_type, target):
     if dilation[0] < 1:
         raise ValueError("dilation should be a positive value")
 
-    isa = arm_isa.IsaAnalyzer(target)
-
     if kernel_layout == "WOI":
-        if layout == "NWC" and isa.has_dsp_support:
+        if layout == "NWC" and target.features.has_dsp:
             strategy.add_implementation(
                 wrap_compute_conv1d(topi.arm_cpu.conv1d_nwc_dsp),
                 wrap_topi_schedule(topi.arm_cpu.schedule_conv1d_nwc_dsp),

tests/micro/zephyr/test_zephyr.py

@@ -32,7 +32,6 @@
 from tvm.relay.testing import byoc
 from tvm.contrib import utils
 from tvm.micro.testing.utils import check_tune_log
-from tvm.target import arm_isa
 
 import test_utils
 
@@ -549,8 +548,7 @@ def test_schedule_build_with_cmsis_dependency(
     build_config = {"debug": microtvm_debug}
     target = tvm.target.target.micro(model, options=["-keys=arm_cpu,cpu"])
 
-    isa = arm_isa.IsaAnalyzer(target)
-    if not isa.has_dsp_support:
+    if not target.features.has_dsp:
         pytest.skip(f"ISA does not support DSP. target: {target}")
 
     # Create a Relay conv2d