[fpv] prim_secded FPV testbench updates bind file naming

The prim_secded related testbench's assertion binds on tb instead of the actual design, so we need to update the bind name. This PR also adds a missing FPV target in batch hjson cfg. Signed-off-by: Cindy Chen <chencindy@opentitan.org>
antmicro · Oct 19, 2021 · 9042945 · 9042945
1 parent 9ab2ce8
commit 9042945
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Showing 9 changed files with 16 additions and 8 deletions.
diff --git a/hw/ip/prim/fpv/tb/prim_secded_22_16_bind_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_22_16_bind_fpv.sv
@@ -6,7 +6,7 @@
 
 module prim_secded_22_16_bind_fpv;
 
-  bind prim_secded_22_16_fpv
+  bind prim_secded_22_16_tb
     prim_secded_22_16_assert_fpv prim_secded_22_16_assert_fpv (
     .clk_i,
     .rst_ni,

diff --git a/hw/ip/prim/fpv/tb/prim_secded_28_22_bind_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_28_22_bind_fpv.sv
@@ -6,7 +6,7 @@
 
 module prim_secded_28_22_bind_fpv;
 
-  bind prim_secded_28_22_fpv
+  bind prim_secded_28_22_tb
     prim_secded_28_22_assert_fpv prim_secded_28_22_assert_fpv (
     .clk_i,
     .rst_ni,

diff --git a/hw/ip/prim/fpv/tb/prim_secded_39_32_bind_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_39_32_bind_fpv.sv
@@ -6,7 +6,7 @@
 
 module prim_secded_39_32_bind_fpv;
 
-  bind prim_secded_39_32_fpv
+  bind prim_secded_39_32_tb
     prim_secded_39_32_assert_fpv prim_secded_39_32_assert_fpv (
     .clk_i,
     .rst_ni,

diff --git a/hw/ip/prim/fpv/tb/prim_secded_64_57_bind_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_64_57_bind_fpv.sv
@@ -6,7 +6,7 @@
 
 module prim_secded_64_57_bind_fpv;
 
-  bind prim_secded_64_57_fpv
+  bind prim_secded_64_57_tb
     prim_secded_64_57_assert_fpv prim_secded_64_57_assert_fpv (
     .clk_i,
     .rst_ni,

diff --git a/hw/ip/prim/fpv/tb/prim_secded_72_64_bind_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_72_64_bind_fpv.sv
@@ -6,7 +6,7 @@
 
 module prim_secded_72_64_bind_fpv;
 
-  bind prim_secded_72_64_fpv
+  bind prim_secded_72_64_tb
     prim_secded_72_64_assert_fpv prim_secded_72_64_assert_fpv (
     .clk_i,
     .rst_ni,

diff --git a/hw/ip/prim/fpv/tb/prim_secded_hamming_22_16_bind_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_hamming_22_16_bind_fpv.sv
@@ -6,7 +6,7 @@
 
 module prim_secded_hamming_22_16_bind_fpv;
 
-  bind prim_secded_hamming_22_16_fpv
+  bind prim_secded_hamming_22_16_tb
     prim_secded_hamming_22_16_assert_fpv prim_secded_hamming_22_16_assert_fpv (
     .clk_i,
     .rst_ni,

diff --git a/hw/ip/prim/fpv/tb/prim_secded_hamming_39_32_bind_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_hamming_39_32_bind_fpv.sv
@@ -6,7 +6,7 @@
 
 module prim_secded_hamming_39_32_bind_fpv;
 
-  bind prim_secded_hamming_39_32_fpv
+  bind prim_secded_hamming_39_32_tb
     prim_secded_hamming_39_32_assert_fpv prim_secded_hamming_39_32_assert_fpv (
     .clk_i,
     .rst_ni,

diff --git a/hw/ip/prim/fpv/tb/prim_secded_hamming_72_64_bind_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_hamming_72_64_bind_fpv.sv
@@ -6,7 +6,7 @@
 
 module prim_secded_hamming_72_64_bind_fpv;
 
-  bind prim_secded_hamming_72_64_fpv
+  bind prim_secded_hamming_72_64_tb
     prim_secded_hamming_72_64_assert_fpv prim_secded_hamming_72_64_assert_fpv (
     .clk_i,
     .rst_ni,

diff --git a/hw/top_earlgrey/formal/top_earlgrey_fpv_cfgs.hjson b/hw/top_earlgrey/formal/top_earlgrey_fpv_cfgs.hjson
@@ -146,6 +146,14 @@
                rel_path: "hw/ip/prim/prim_secded_39_32/{sub_flow}/{tool}"
                cov: true
              }
+             {
+               name: prim_secded_64_57_fpv
+               dut: prim_secded_64_57_tb
+               fusesoc_core: lowrisc:fpv:prim_secded_64_57_fpv
+               import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"]
+               rel_path: "hw/ip/prim/prim_secded_64_57/{sub_flow}/{tool}"
+               cov: true
+             }
              {
                name: prim_secded_72_64_fpv
                dut: prim_secded_72_64_tb