Stage w logic WIP

rtl/letc/core/letc_core_stage_w.sv

@@ -4,6 +4,7 @@
  *
  * Copyright:
  *  Copyright (C) 2024 John Jekel
+ *  Copyright (C) 2024 Sam Graham
  * See the LICENSE file at the root of the project for licensing info.
  *
  * TODO longer description
@@ -19,26 +20,26 @@ module letc_core_stage_w
     import letc_core_pkg::*;
 (
     //Clock and reset
-    input logic i_clk,
-    input logic i_rst_n,
+    input  logic        i_clk,                  // todo
+    input  logic        i_rst_n,                // todo
 
     //TODO
 
     //Hazard/backpressure signals
-    output logic o_stage_ready,
-    input  logic i_stage_flush,
-    input  logic i_stage_stall,
+    output logic        o_stage_ready,
+    input  logic        i_stage_flush,          // todo
+    input  logic        i_stage_stall,          // todo
 
     //rd Write Port
-    output reg_idx_t    o_rd_idx,
+    output reg_idx_t    o_rd_idx,               // todo
     output word_t       o_rd_wdata,
-    output logic        o_rd_wen,
+    output logic        o_rd_wen,               // todo
 
     //CSR Write Port
     output logic        o_csr_explicit_wen,
     output csr_idx_t    o_csr_explicit_widx,
     output word_t       o_csr_explicit_wdata,
-    input  logic        i_csr_explicit_will,
+    input  logic        i_csr_explicit_will,    // todo
 
     //From E2
     input  e2_to_w_s    i_e2_to_w
@@ -47,4 +48,18 @@ module letc_core_stage_w
 logic todo;
 assign o_stage_ready = 1'b1;
 
+assign o_csr_explicit_wdata = i_e2_to_w.alu_result;
+assign o_csr_explicit_widx  = i_e2_to_w.csr_idx;
+
+always_comb begin : rd_mux
+    unique case (rd_src)
+        RD_FROM_NEXT_SEQ_PC:    o_rd_wdata = 0;
+        RD_FROM_ALU_RESULT:     o_rd_wdata = i_e2_to_w.alu_result;
+        RD_FROM_CSR:            o_rd_wdata = i_e2_to_w.old_csr_value;
+        RD_FROM_MEM_LOAD:       o_rd_wdata = i_e2_to_w.memory_rdata;
+    endcase
+end : rd_mux
+
+assign o_csr_explicit_wen = (i_e2_to_w.csr_op == CSR_OP_ACCESS) ? 1 : 0;
+
 endmodule : letc_core_stage_w