Updated NI version. Now NI set the header based on memory mapped regi…

…sters.

rtl/network-interfaces/orca-ni/orca-ni-recv-Nflit.vhd

@@ -232,14 +232,14 @@ begin
           recv_copy_size <= (others => '1');
           stall <= '0'; --enable cpu to use memory until next packet arrival
           recv_copy_addr <= (others => '0');
-          if r_rx = '1' then
-            recv_copy_addr <= recv_copy_addr + 1; --advance mem. to 2nd position
-          end if;
+--          if r_rx = '1' then
+--            recv_copy_addr <= recv_copy_addr + 1; --advance mem. to 2nd position
+--          end if;
 
         -- wait for the size flit to arrive
         when R_WAIT_FLIT_SIZE => 
           if r_rx = '1' then
-            recv_copy_addr <= recv_copy_addr + 1; --advances mem ptr.
+--            recv_copy_addr <= recv_copy_addr + 1; --advances mem ptr.
             recv_copy_size <= size(TAM_FLIT-1 downto 0) - 1;
             recv_status <= size(RAM_WIDTH/2 - 1 downto 0); -- notify recv flits to cpu
           end if;

rtl/network-interfaces/orca-ni/orca-ni-send-Nflit.vhd

@@ -28,6 +28,7 @@ entity orca_ni_send is
     -- dma programming (must be mapped into memory space)
     send_start : in std_logic;
     prog_address : in std_logic_vector((RAM_WIDTH - 1) downto 0);
+    prog_dest    : in std_logic_vector((RAM_WIDTH - 1) downto 0);
     prog_size    : in std_logic_vector((RAM_WIDTH - 1) downto 0);
     send_status : out std_logic
   );
@@ -152,16 +153,16 @@ end process;
         when S_SEND_DESTINY => 
           if r_credit_i = '1' then
              r_tx <= '1';
-             send_copy_size <= send_copy_size - 1;
-             send_copy_addr <= send_copy_addr + 4;
-             send_copy_addr_dly <= send_copy_addr;
+--             send_copy_size <= send_copy_size - 1;
+--             send_copy_addr <= send_copy_addr + 4;
+--             send_copy_addr_dly <= send_copy_addr;
           end if;
 
         when S_SEND_SIZE => 
           if r_credit_i = '1' then
-             send_copy_size <= send_copy_size - 1;
-             send_copy_addr <= send_copy_addr + 4;
-             send_copy_addr_dly <= send_copy_addr;
+--             send_copy_size <= send_copy_size - 1;
+--             send_copy_addr <= send_copy_addr + 4;
+--             send_copy_addr_dly <= send_copy_addr;
           end if;
 
         when S_PAYLOAD => --copy from memory to the output buffer
@@ -206,7 +207,7 @@ end process;
     mux(i) <= m_data_i((TAM_FLIT*(i+1)) - 1 downto (TAM_FLIT*i)) when send_state = S_PAYLOAD else (others => '0');
   end generate;
 
-  r_data_o <= half_flit_complement & m_data_i(RAM_WIDTH/4+TAM_FLIT/4-1 downto RAM_WIDTH/4) & m_data_i(TAM_FLIT/4-1 downto 0) when previous_state = S_SEND_DESTINY else m_data_i(TAM_FLIT-INTEGER(CEIL(LOG2(REAL(RAM_WIDTH/TAM_FLIT))))-1 downto 0) & shift when previous_state = S_SEND_SIZE else mux(to_integer(unsigned(shift))) when previous_state = S_PAYLOAD else (others => '0');
+  r_data_o <= half_flit_complement & prog_dest(RAM_WIDTH/4+TAM_FLIT/4-1 downto RAM_WIDTH/4) & prog_dest(TAM_FLIT/4-1 downto 0) when previous_state = S_SEND_DESTINY else prog_size(TAM_FLIT-INTEGER(CEIL(LOG2(REAL(RAM_WIDTH/TAM_FLIT))))-1 downto 0) & shift when previous_state = S_SEND_SIZE else mux(to_integer(unsigned(shift))) when previous_state = S_PAYLOAD else (others => '0');
 
   stall <= r_stall;  
 

rtl/network-interfaces/orca-ni/orca-ni-top.vhd

@@ -38,6 +38,7 @@ entity orca_ni_top is
     recv_start : in std_logic;
     send_status : out std_logic;
     recv_status : out std_logic_vector((RAM_WIDTH/2 - 1) downto 0);
+    prog_dest    : in std_logic_vector((RAM_WIDTH - 1) downto 0);
     prog_address : in std_logic_vector((RAM_WIDTH - 1) downto 0);
     prog_size    : in std_logic_vector((RAM_WIDTH - 1) downto 0)
 
@@ -80,6 +81,7 @@ begin
       send_status => send_status_s,
 
       prog_address => prog_address,
+      prog_dest => prog_dest,
       prog_size => prog_size
     );
 

rtl/orca-minimal-soc.vhd

@@ -6,7 +6,7 @@
 --
 -- Very simple configuration for a minimal SoC. Only a single GPIO port
 -- a counter and timer are included in this version.
--- NI: registradores: NI_ADDRESS (0xe0ff8000), NI_STATUS (0xe0ff8010), NI_MEM_ADDR (0xe0ff8020), NI_PCT_SIZE (0xe0ff8030)
+-- NI: registradores: NI_ADDRESS (0xe0ff8000), NI_STATUS (0xe0ff8010), NI_MEM_ADDR (0xe0ff8020), NI_PCT_SIZE (0xe0ff8030), NI_PCT_DEST (0xe0ff8040)
 
 
 
@@ -38,7 +38,8 @@ entity peripherals is
 		ni_intr : in std_logic;
 		ni_recv_size : in std_logic_vector((RAM_WIDTH/2 - 1) downto 0);
 		ni_mem_addr : out std_logic_vector((RAM_WIDTH - 1) downto 0);
-		ni_pct_size : out std_logic_vector((RAM_WIDTH - 1) downto 0)
+		ni_pct_size : out std_logic_vector((RAM_WIDTH - 1) downto 0);
+		ni_pct_dest : out std_logic_vector((RAM_WIDTH - 1) downto 0)
 	);
 end peripherals;
 
@@ -50,7 +51,7 @@ architecture peripherals_arch of peripherals is
 
 	signal paaltcfg0, s0cause, gpiocause, gpiocause_inv, gpiomask, timercause, timercause_inv, timermask: std_logic_vector(3 downto 0);
 	signal paddr, paout, pain, pain_inv, pain_mask: std_logic_vector(7 downto 0);
-	signal timer0, ni_addr, ni_size : std_logic_vector(31 downto 0);
+	signal timer0, ni_addr, ni_size, ni_dest : std_logic_vector(31 downto 0);
 	signal timer1, timer1_ctc, timer1_ocr: std_logic_vector(15 downto 0);
 	signal timer1_pre: std_logic_vector(2 downto 0);
 	signal timer1_set: std_logic;
@@ -91,6 +92,7 @@ begin
 	ni_reload <= ni_reld;
 	ni_mem_addr <= ni_addr;
 	ni_pct_size <= ni_size;
+	ni_pct_dest <= ni_dest;
 
 	-- address decoder, read from peripheral registers
 	process(clk_i, rst_i, segment, class, device, funct)
@@ -114,6 +116,8 @@ begin
 								data_o <= ni_addr;										-- NI_MEM_ADDR		(RW)
 							when "0011" =>
 								data_o <= ni_size;										-- NI_PCT_SIZE		(RW)
+							when "0100" =>
+								data_o <= ni_dest;										-- NI_PCT_DEST		(RW)
 							when others =>
 								data_o <= (others => '0');
 							end case;
@@ -221,6 +225,7 @@ begin
 			ni_recv_strt <= '0';
 			ni_addr <= (others => '0');
 			ni_size <= (others => '0');
+			ni_dest <= (others => '0');
 		elsif clk_i'event and clk_i = '1' then
 			if sel_i = '1' and wr_i = '1' then
 				case segment is
@@ -238,6 +243,8 @@ begin
 								ni_addr <= data_i;			-- NI_MEM_ADDR		(RW)
 							when "0011" =>
 								ni_size <= data_i;			-- NI_PCT_SIZE		(RW)
+							when "0100" =>
+								ni_dest <= data_i;			-- NI_PCT_DEST		(RW)
 							when others =>
 							end case;
 						when others =>

rtl/orca-tile-proc.vhd

@@ -67,6 +67,7 @@ architecture orca_processing_tile of orca_processing_tile is
   signal recv_status :  std_logic_vector(((RAM_WIDTH/2) - 1) downto 0);
   signal prog_address : std_logic_vector((RAM_WIDTH - 1) downto 0);
   signal prog_size    : std_logic_vector((RAM_WIDTH - 1) downto 0);
+  signal prog_dest    : std_logic_vector((RAM_WIDTH - 1) downto 0);
 
   signal n_addr_o : std_logic_vector((RAM_WIDTH - 1) downto 0);
   signal n_data_o : std_logic_vector((RAM_WIDTH - 1) downto 0);
@@ -204,7 +205,8 @@ begin
       ni_intr => ni_intr,
       ni_recv_size => recv_status,
       ni_mem_addr => prog_address,
-      ni_pct_size => prog_size
+      ni_pct_size => prog_size,
+      ni_pct_dest => prog_dest
 
     );
 
@@ -279,6 +281,7 @@ begin
       send_status => send_status,
       recv_status => recv_status,
       prog_address => prog_address,
+      prog_dest => prog_dest,
       prog_size => prog_size
     );