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fix(CMSIS): MSDK-1249: Add OVR Correction to SystemCoreClock Calculation for MAX32662 MAX32672 MAX32675 #867

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merged 1 commit into from
Jan 13, 2024
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fix(CMSIS): MSDK-1249: Add OVR Correction to SystemCoreClock Calculation for MAX32662 MAX32672 MAX32675 #867

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21 changes: 21 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c
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Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@
#include <stdlib.h>
#include "max32662.h"
#include "gcr_regs.h"
#include "pwrseq_regs.h"
#include "mxc_sys.h"

extern void (*const __isr_vector[])(void);
Expand Down Expand Up @@ -82,6 +83,26 @@ __weak void SystemCoreClockUpdate(void)
break;
}

if (clk_src == MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO) {
uint32_t ovr = (MXC_PWRSEQ->lpctrl & MXC_F_PWRSEQ_LPCTRL_OVR);
switch (ovr) {
case MXC_S_PWRSEQ_LPCTRL_OVR_0_9V:
base_freq = base_freq >> 3;
break;
case MXC_S_PWRSEQ_LPCTRL_OVR_1_0V:
base_freq = base_freq >> 1;
break;
case MXC_S_PWRSEQ_LPCTRL_OVR_1_1V:
default:
/* Nothing to do here.
OVR = 1.1V means the clock runs full speed. */
break;
}
// Get the clock divider
base_freq = base_freq >> ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_DIV) >>
MXC_F_GCR_CLKCTRL_IPO_DIV_POS);
}

div = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV) >> MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS;

SystemCoreClock = base_freq >> div;
Expand Down
16 changes: 16 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c
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Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,7 @@
#include "max32672.h"
#include "gcr_regs.h"
#include "mxc_sys.h"
#include "pwrseq_regs.h"

extern void (*const __isr_vector[])(void);

Expand Down Expand Up @@ -78,6 +79,21 @@ __weak void SystemCoreClockUpdate(void)
}
// Get the clock divider
if (clk_src == MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO) {
uint32_t ovr = (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_OVR);
switch (ovr) {
case MXC_S_PWRSEQ_LPCN_OVR_0_9V:
base_freq = base_freq >> 3;
break;
case MXC_S_PWRSEQ_LPCN_OVR_1_0V:
base_freq = base_freq >> 1;
break;
case MXC_S_PWRSEQ_LPCN_OVR_1_1V:
default:
/* Nothing to do here.
OVR = 1.1V means the clock runs full speed. */
break;
}

base_freq = base_freq >> ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_DIV) >>
MXC_F_GCR_CLKCTRL_IPO_DIV_POS);
}
Expand Down
16 changes: 16 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c
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Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,7 @@
#include "max32675.h"
#include "gcr_regs.h"
#include "mxc_sys.h"
#include "pwrseq_regs.h"

extern void (*const __vector_table[])(void);

Expand Down Expand Up @@ -80,6 +81,21 @@ __weak void SystemCoreClockUpdate(void)
}
// Get the clock divider
if (clk_src == MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO) {
uint32_t ovr = (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_OVR);
switch (ovr) {
case MXC_S_PWRSEQ_LPCN_OVR_0_9V:
base_freq = base_freq >> 3;
break;
case MXC_S_PWRSEQ_LPCN_OVR_1_0V:
base_freq = base_freq >> 1;
break;
case MXC_S_PWRSEQ_LPCN_OVR_1_1V:
default:
/* Nothing to do here.
OVR = 1.1V means the clock runs full speed. */
break;
}

base_freq = base_freq >> ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_DIV) >>
MXC_F_GCR_CLKCTRL_IPO_DIV_POS);
}
Expand Down
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