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fix(CMSIS): Match clock/trim settings in SYS registers to latest changes for MAX32657 #320

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fix(CMSIS): Match clock/trim settings in SYS registers to latest changes for MAX32657

fix(CMSIS): Match clock/trim settings in SYS registers to latest changes for MAX32657 #320

Triggered via pull request October 2, 2024 21:13
@sihyung-maximsihyung-maxim
synchronize #1183
feat/me30_fcr
Status Failure
Total duration 3m 39s
Artifacts –

example_tester.yml

on: pull_request
Example_Tests_MAX32690
33s
Example_Tests_MAX32690
Example_Tests_MAX78002
2m 52s
Example_Tests_MAX78002
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1 error
Example_Tests_MAX32690
Process completed with exit code 2.