iio: frequency: ad9783: fix calibration array values #2608
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Run loop in accordance with the method described in section "building the array" of the datasheet[1] rev C. page 26. The loop shall be continued until the seek bit toggles, not until the seek bit goes low. For the case where a value for SET or HLD is not found that would make the SEEK bit toggle, the value should be set to 15. The loop did not break out until HLD == 16, causing overflowing value to be written to the HLD field[0..3] of register 0x4. [1] https://www.analog.com/media/en/technical-documentation/data-sheets/AD9780_9781_9783.pdf Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
vai-tomme
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nunojsa,
mhennerich,
dbogdan,
btogorean,
chegbeli,
buha,
amiclaus,
rbolboac,
danmois,
CiprianRegus and
machschmitt
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nunojsa
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Oct 4, 2024
| @@ -250,7 +249,7 @@ static int ad9783_timing_adjust(struct ad9783_phy *phy) | |||
| if (ret < 0) | |||
| return ret; | |||
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| } while (ret > 0 && set < AD9783_MAX_SET); | |||
| } while ((ret == table[smp][SEEK]) && set < (AD9783_MAX_SET - 1)); | |||
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nit: You don't need the extra parenthesis...
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checkpatch did not complain, and I find it somewhat more readable like this. So if OK with You, I would keep it as is.
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PR Description
Run loop in accordance with the method described in section "building the array" of the datasheet[1] rev C. page 26. The loop shall be continued until the seek bit toggles, not until the seek bit goes low.
For the case where a value for SET or HLD is not found that would make the SEEK bit toggle, the value should be set to 15. The loop did not break out until HLD == 16, causing overflowing value to be written to the HLD field[0..3] of register 0x4.
[1] https://www.analog.com/media/en/technical-documentation/data-sheets/AD9780_9781_9783.pdf
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