hdl_2016_r2

Change log:

1. Supported tools version for this release are:
   • Vivado 2016.2
   • Quartus 16.0
2. Major updates:
   • IP cores that are specific to FPGA devices are moved into their own respective folders (altera/xilinx)
   • The JESD transceiver frame work has changed. The IP cores now support asymmetrical lane sharing across transmit and receive links while supporting dynamic reconfiguration. The Xilinx projects, the ADI transceiver cores may now be replaced with Xilinx JESD PHY IP at the expense of Eye Scan function.
   • The AD9361 IP core for Altera supports 1R1T mode as well as separate clock, receive and transmit primitives. The core supports both Cyclone V and Arria 10 devices.
   • Additional features added to axi_ad9361 IP core:
     • CMOS support
     • New parameters for finer data path configuration
     • TDD support, with optional ENABLE/TXNRX pin control by software.
   • Altera support for axi_ad9152
   • Add xilinx/axi_dacfifo for high speed DAC paths
3. Library changes:
   • Added new IP cores:
     • util_adxcvr
     • avl_adxcvr
     • axi_adxcvr
     • axi_ad9684
     • axi_ad9162
     • axi_ad7616
   • Removed obsolete and unsupported cores:
     • util_jesd_gt
     • util_gtlb
     • axi_jesd_gt
4. Project changes:
   • Supports Arria 10 SOC, Zynq MP SOC Ultrascale+ devices
   • DAQ1: add CPLD logic and new ADC core (axi_ad9684)
   • PZSDR moved to PZSDR2
   • FMCOMMS2: add support for A10GX and ZCU102
   • Removed obsolete and unsupported projects
     • FMCOMMS6
   • New projects:
     • ADRV9371X
     • FMCOMMS11
     • PZSDR1
     • PLUTO
     • USRPE31X
5. Unsupported or in development projects (do NOT use):
   • The FMCOMMS2 projects on Arria 10 devices is provided as a template ONLY. The project will NOT work on hardware (A10GX or A10SOC) due to Altera's lack of knowledge on their device bank/FMC pin assignments.
   • CFTL_CIP and CFTL_STD
   • FMCOMMS2 ZC706 Partial Reconfiguration (zc706pr)