Dev quad ad77681

[sarpadi]

HDL for PMB00004 board

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones

[sarpadi]

Hi @dlech. This PR includes changes to the axi_spi_engine IP core that aim to provide FIFO mode support for multiple SDI lines. This means that we have to add extra registers and we also had to move some of the existing ones to get a better usage of address space. Any feedback would be nice.

https://github.com/analogdevicesinc/hdl/pull/1490/files#diff-d1274cfe2e206aa66a0ecd3da04b3e62fc5fad9e12029b34b226c6f91454d34d
https://github.com/analogdevicesinc/hdl/pull/1490/files#diff-05633a28329dff91191debd876bef07f0693c441d2af021d4b8c82e3f0d44aff