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ad9213-evb/vcu118 reference design #1135

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Aug 14, 2023
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ad9213-evb/vcu118 reference design #1135

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6c343d4
ad9213_evb: Initial commit
FilipG24 Mar 24, 2022
fe9af45
ad9213_evb: Add design
AndrDragomir Jan 11, 2023
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7 changes: 7 additions & 0 deletions projects/ad9213_evb/Makefile
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###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
###############################################################################

include ../scripts/project-toplevel.mk
8 changes: 8 additions & 0 deletions projects/ad9213_evb/Readme.md
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# AD9213 EVB HDL Project

Here are some pointers to help you:
* [Board Product Page](https://www.analog.com/eval-ad9213)
* Parts : [12-Bit, 10.25 GSPS, JESD204B, RF Analog-to-Digital Converter](https://www.analog.com/en/products/ad9213.html)
* Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad9213_evb/start
* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad9213_evb/ad9213_evb_hdl
* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all
170 changes: 170 additions & 0 deletions projects/ad9213_evb/common/ad9213_evb_bd.tcl
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###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

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# RX parameters for each converter
set RX_NUM_OF_LANES 16 ; # L
set RX_NUM_OF_CONVERTERS 1 ; # M
set RX_SAMPLES_PER_FRAME 16 ; # S
set RX_SAMPLE_WIDTH 16 ; # N/NP

set RX_SAMPLES_PER_CHANNEL 32 ; # L * 32 / (M * N)

source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl

set adc_fifo_name axi_ad9213_fifo
set adc_data_width 512
set adc_dma_data_width 512

create_bd_port -dir I glbl_clk_0

create_bd_port -dir O -from 1 -to 0 hmc7044_csn_o
create_bd_port -dir I -from 1 -to 0 hmc7044_csn_i
create_bd_port -dir I hmc7044_clk_i
create_bd_port -dir O hmc7044_clk_o
create_bd_port -dir I hmc7044_sdo_i
create_bd_port -dir O hmc7044_sdo_o
create_bd_port -dir I hmc7044_sdi_i

# adc peripherals

ad_ip_instance util_adxcvr util_adc_xcvr
ad_ip_parameter util_adc_xcvr CONFIG.CPLL_FBDIV_4_5 5
ad_ip_parameter util_adc_xcvr CONFIG.TX_NUM_OF_LANES 0
ad_ip_parameter util_adc_xcvr CONFIG.RX_NUM_OF_LANES 16
ad_ip_parameter util_adc_xcvr CONFIG.RX_LANE_INVERT 390
ad_ip_parameter util_adc_xcvr CONFIG.RX_OUT_DIV 1

ad_ip_instance axi_adxcvr axi_ad9213_xcvr
ad_ip_parameter axi_ad9213_xcvr CONFIG.ID 0
ad_ip_parameter axi_ad9213_xcvr CONFIG.NUM_OF_LANES 16
ad_ip_parameter axi_ad9213_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_ad9213_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_ad9213_xcvr CONFIG.LPM_OR_DFE_N 1
ad_ip_parameter axi_ad9213_xcvr CONFIG.SYS_CLK_SEL 0x3

adi_axi_jesd204_rx_create axi_ad9213_jesd 16
ad_ip_parameter axi_ad9213_jesd/rx CONFIG.SYSREF_IOB false
ad_ip_parameter axi_ad9213_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2

adi_tpl_jesd204_rx_create rx_ad9213_tpl_core $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH

ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width

ad_ip_instance axi_dmac axi_ad9213_dma
ad_ip_parameter axi_ad9213_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad9213_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad9213_dma CONFIG.ID 0
ad_ip_parameter axi_ad9213_dma CONFIG.AXI_SLICE_SRC 1
ad_ip_parameter axi_ad9213_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad9213_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad9213_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9213_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9213_dma CONFIG.MAX_BYTES_PER_BURST 4096
ad_ip_parameter axi_ad9213_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9213_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width
ad_ip_parameter axi_ad9213_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_dma_data_width

# reference clocks & resets

create_bd_port -dir I rx_ref_clk_0
create_bd_port -dir I rx_ref_clk_1

ad_xcvrpll rx_ref_clk_0 util_adc_xcvr/qpll_ref_clk_0
ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/qpll_ref_clk_4
ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/qpll_ref_clk_8
ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/qpll_ref_clk_12

ad_xcvrpll rx_ref_clk_0 util_adc_xcvr/cpll_ref_clk_0
ad_xcvrpll rx_ref_clk_0 util_adc_xcvr/cpll_ref_clk_1
ad_xcvrpll rx_ref_clk_0 util_adc_xcvr/cpll_ref_clk_2
ad_xcvrpll rx_ref_clk_0 util_adc_xcvr/cpll_ref_clk_3
ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_4
ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_5
ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_6
ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_7
ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_8
ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_9
ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_10
ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_11
ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_12
ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_13
ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_14
ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_15

ad_xcvrpll axi_ad9213_xcvr/up_pll_rst util_adc_xcvr/up_qpll_rst_*
ad_xcvrpll axi_ad9213_xcvr/up_pll_rst util_adc_xcvr/up_cpll_rst_*

ad_connect $sys_cpu_resetn util_adc_xcvr/up_rstn
ad_connect $sys_cpu_clk util_adc_xcvr/up_clk

# connections (adc)

ad_xcvrcon util_adc_xcvr axi_ad9213_xcvr axi_ad9213_jesd {4 0 2 1 3 8 9 7 6 11 10 15 12 14 13 5} glbl_clk_0

## use global clock as device clock instead of rx_out_clk
delete_bd_objs [get_bd_nets util_adc_xcvr_rx_out_clk_0]

# connect clocks
# device clock domain
ad_connect glbl_clk_0 rx_ad9213_tpl_core/link_clk

ad_connect glbl_clk_0 axi_ad9213_fifo/adc_clk

# dma clock domain
ad_connect $sys_cpu_clk axi_ad9213_fifo/dma_clk
ad_connect $sys_cpu_clk axi_ad9213_dma/s_axis_aclk

# connect resets
ad_connect glbl_clk_0_rstgen/peripheral_reset axi_ad9213_fifo/adc_rst
ad_connect $sys_cpu_resetn axi_ad9213_dma/m_dest_axi_aresetn

# connect dataflow
ad_connect axi_ad9213_jesd/rx_sof rx_ad9213_tpl_core/link_sof
ad_connect axi_ad9213_jesd/rx_data_tdata rx_ad9213_tpl_core/link_data
ad_connect axi_ad9213_jesd/rx_data_tvalid rx_ad9213_tpl_core/link_valid

ad_connect rx_ad9213_tpl_core/adc_valid_0 axi_ad9213_fifo/adc_wr
ad_connect rx_ad9213_tpl_core/adc_data_0 axi_ad9213_fifo/adc_wdata

ad_connect rx_ad9213_tpl_core/adc_dovf axi_ad9213_fifo/adc_wovf

ad_connect axi_ad9213_fifo/dma_wr axi_ad9213_dma/s_axis_valid
ad_connect axi_ad9213_fifo/dma_wdata axi_ad9213_dma/s_axis_data
ad_connect axi_ad9213_fifo/dma_wready axi_ad9213_dma/s_axis_ready
ad_connect axi_ad9213_fifo/dma_xfer_req axi_ad9213_dma/s_axis_xfer_req

ad_ip_instance axi_quad_spi hmc7044_spi
ad_ip_parameter hmc7044_spi CONFIG.C_USE_STARTUP 0
ad_ip_parameter hmc7044_spi CONFIG.C_NUM_SS_BITS 2
ad_ip_parameter hmc7044_spi CONFIG.C_SCK_RATIO 8

ad_connect hmc7044_csn_i hmc7044_spi/ss_i
ad_connect hmc7044_csn_o hmc7044_spi/ss_o
ad_connect hmc7044_clk_i hmc7044_spi/sck_i
ad_connect hmc7044_clk_o hmc7044_spi/sck_o
ad_connect hmc7044_sdo_i hmc7044_spi/io0_i
ad_connect hmc7044_sdo_o hmc7044_spi/io0_o
ad_connect hmc7044_sdi_i hmc7044_spi/io1_i

ad_connect $sys_cpu_clk hmc7044_spi/ext_spi_clk

# interconnect (cpu)
ad_cpu_interconnect 0x44a60000 axi_ad9213_xcvr
ad_cpu_interconnect 0x44a10000 rx_ad9213_tpl_core
ad_cpu_interconnect 0x44a90000 axi_ad9213_jesd
ad_cpu_interconnect 0x44a71000 hmc7044_spi
ad_cpu_interconnect 0x7c420000 axi_ad9213_dma

# interconnect (gt/adc)
ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9213_xcvr/m_axi
ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9213_dma/m_dest_axi

# interrupts
ad_cpu_interrupt ps-17 mb-7 hmc7044_spi/ip2intc_irpt
ad_cpu_interrupt ps-12 mb-12 axi_ad9213_dma/irq
ad_cpu_interrupt ps-11 mb-13 axi_ad9213_jesd/irq
71 changes: 71 additions & 0 deletions projects/ad9213_evb/common/ad9213_evb_fmc.txt
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FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
# ad9213_evb

D4 GBTCLK0_M2C_P FMC_P1_GBTCLK0M2C_P rx_ref_clk_p #N/A #N/A
D5 GBTCLK0_M2C_N FMC_P1_GBTCLK0M2C_N rx_ref_clk_n #N/A #N/A
D4 GBTCLK0_M2C_P FMC_P1_GBTCLK0M2C_P rx_ref_clk_replica_p #N/A #N/A
D5 GBTCLK0_M2C_N FMC_P1_GBTCLK0M2C_N rx_ref_clk_replica_n #N/A #N/A

L12 GBTCLK2_M2C_P FMC_P1_GBTCLK2M2C_P glbl_clk_0_p #N/A #N/A
L13 GBTCLK2_M2C_N FMC_P1_GBTCLK2M2C_N glbl_clk_0_n #N/A #N/A

H7 LA02_P LA02_P rx_sysref_p LVDS DIFF_TERM_ADV TERM_100
H8 LA02_N LA02_N rx_sysref_n LVDS DIFF_TERM_ADV TERM_100
H10 LA04_P AD9213_0_SYNCINB_P rx_sync_p LVDS #N/A
H11 LA04_N AD9213_0_SYNCINB_N rx_sync_n LVDS #N/A

A14 DP4_M2C_P DOUT_P0 rx_data_p[0] #N/A #N/A
A15 DP4_M2C_N DOUT_N0 rx_data_n[0] #N/A #N/A
C6 DP0_M2C_P DOUT_P1 rx_data_p[1] #N/A #N/A
C7 DP0_M2C_N DOUT_N1 rx_data_n[1] #N/A #N/A
A6 DP2_M2C_P DOUT_N2 rx_data_p[2] #N/A #N/A
A7 DP2_M2C_N DOUT_P2 rx_data_n[2] #N/A #N/A
A2 DP1_M2C_P DOUT_N3 rx_data_p[3] #N/A #N/A
A3 DP1_M2C_N DOUT_P3 rx_data_n[3] #N/A #N/A
A10 DP3_M2C_P DOUT_P4 rx_data_p[4] #N/A #N/A
A11 DP3_M2C_N DOUT_N4 rx_data_n[4] #N/A #N/A
Y14 DP12_M2C_P DOUT_N5 rx_data_p[5] #N/A #N/A
Y15 DP12_M2C_N DOUT_P5 rx_data_n[5] #N/A #N/A
Z16 DP13_M2C_P DOUT_P6 rx_data_p[6] #N/A #N/A
Z17 DP13_M2C_N DOUT_N6 rx_data_n[6] #N/A #N/A
B12 DP7_M2C_P DOUT_N7 rx_data_p[7] #N/A #N/A
B13 DP7_M2C_N DOUT_P7 rx_data_n[7] #N/A #N/A
B16 DP6_M2C_P DOUT_P8 rx_data_p[8] #N/A #N/A
B17 DP6_M2C_N DOUT_N8 rx_data_n[8] #N/A #N/A
Y22 DP15_M2C_P DOUT_P9 rx_data_p[9] #N/A #N/A
Y23 DP15_M2C_N DOUT_N9 rx_data_n[9] #N/A #N/A
Y18 DP14_M2C_P DOUT_P10 rx_data_p[10] #N/A #N/A
Y19 DP14_M2C_N DOUT_N10 rx_data_n[10] #N/A #N/A
Y38 DP19_M2C_P DOUT_P11 rx_data_p[11] #N/A #N/A
Y39 DP19_M2C_N DOUT_N11 rx_data_n[11] #N/A #N/A
Z32 DP16_M2C_P DOUT_P12 rx_data_p[12] #N/A #N/A
Z33 DP16_M2C_N DOUT_N12 rx_data_n[12] #N/A #N/A
Z36 DP18_M2C_P DOUT_P13 rx_data_p[13] #N/A #N/A
Z37 DP18_M2C_N DOUT_N13 rx_data_n[13] #N/A #N/A
Y34 DP17_M2C_P DOUT_P14 rx_data_p[14] #N/A #N/A
Y35 DP17_M2C_N DOUT_N14 rx_data_n[14] #N/A #N/A
A18 DP5_M2C_P DOUT_P15 rx_data_p[15] #N/A #N/A
A19 DP5_M2C_N DOUT_N15 rx_data_n[15] #N/A #N/A

D17 LA13_P FPGA_RSTB_0 rstb LVCMOS18 #N/A

G12 LA08_P FPGA_GPIO0_0 gpio[0] LVCMOS18 #N/A
G13 LA08_N FPGA_GPIO1_0 gpio[1] LVCMOS18 #N/A
D14 LA09_P FPGA_GPIO2_0 gpio[2] LVCMOS18 #N/A
D15 LA09_N FPGA_GPIO3_0 gpio[3] LVCMOS18 #N/A
C14 LA10_P FPGA_GPIO4_0 gpio[4] LVCMOS18 #N/A

H13 LA07_P FPGA_CSB0 fpga_csb LVCMOS18 #N/A
C11 LA06_N FPGA_SCLK fpga_sclk LVCMOS18 #N/A
C10 LA06_P FPGA_SDIO fpga_sdio LVCMOS18 #N/A

C18 LA14_P FPGA_HMC7044_CSB hmc7044_csb LVCMOS18 #N/A
C19 LA14_N FPGA_HMC7044_SCLK hmc7044_sclk LVCMOS18 #N/A
H19 LA15_P FPGA_HMC7044_SDI hmc7044_sdio LVCMOS18 #N/A
D18 LA13_N HMC7044_SYNC_REQ_TO_FPGA hmc_sync_req LVCMOS18 #N/A

H22 LA19_P FPGA_ADF4371_0_CSB adf4371_csb LVCMOS18 #N/A
G18 LA16_P FPGA_ADF4371_SCLK adf4371_sclk LVCMOS18 #N/A
G19 LA16_N FPGA_ADF4371_SDIO adf4371_sdio LVCMOS18 #N/A

H20 LA15_N FPGA_LTC6952_0_SDO ltc6952_sdo LVCMOS18 #N/A
28 changes: 28 additions & 0 deletions projects/ad9213_evb/vcu118/Makefile
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###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
###############################################################################

PROJECT_NAME := ad9213_evb_vcu118

M_DEPS += ../common/ad9213_evb_bd.tcl
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
M_DEPS += ../../common/vcu118/vcu118_system_constr.xdc
M_DEPS += ../../common/vcu118/vcu118_system_bd.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_3w_spi.v

LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += sysid_rom
LIB_DEPS += util_adcfifo
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr

include ../../scripts/project-xilinx.mk
38 changes: 38 additions & 0 deletions projects/ad9213_evb/vcu118/system_bd.tcl
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###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

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## FIFO depth is 4Mb - 250k samples (65k samples per converter)
set adc_fifo_address_width 13

source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source ../common/ad9213_evb_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl

# Set SPI clock to 100/16 = 6.25 MHz
ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 16
ad_ip_parameter hmc7044_spi CONFIG.C_SCK_RATIO 16

#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9

sysid_gen_sys_init_file

ad_ip_parameter util_adc_xcvr CONFIG.RX_CLK25_DIV 30
ad_ip_parameter util_adc_xcvr CONFIG.CPLL_CFG0 0x1fa
ad_ip_parameter util_adc_xcvr CONFIG.CPLL_CFG1 0x2b
ad_ip_parameter util_adc_xcvr CONFIG.CPLL_CFG2 0x2
ad_ip_parameter util_adc_xcvr CONFIG.CPLL_FBDIV 2
ad_ip_parameter util_adc_xcvr CONFIG.CH_HSPMUX 0x4040
ad_ip_parameter util_adc_xcvr CONFIG.PREIQ_FREQ_BST 1
ad_ip_parameter util_adc_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5
ad_ip_parameter util_adc_xcvr CONFIG.RXPI_CFG0 0x3002
ad_ip_parameter util_adc_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter util_adc_xcvr CONFIG.QPLL_CFG0 0x333c
ad_ip_parameter util_adc_xcvr CONFIG.QPLL_CFG4 0x2
ad_ip_parameter util_adc_xcvr CONFIG.QPLL_FBDIV 20
ad_ip_parameter util_adc_xcvr CONFIG.PPF0_CFG 0xB00
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