Reverted second part of the license

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
analogdevicesinc · Jul 26, 2023 · c2b0c9a · c2b0c9a
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diff --git a/library/common/tb/tb_base.v b/library/common/tb/tb_base.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2020-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
   reg clk = 1'b0;
   reg [3:0] reset_shift = 4'b1111;

diff --git a/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl b/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl

diff --git a/library/intel/adi_jesd204/adi_jesd204_hw.tcl b/library/intel/adi_jesd204/adi_jesd204_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl

diff --git a/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl b/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl

diff --git a/library/intel/jesd204_phy/jesd204_phy_hw.tcl b/library/intel/jesd204_phy/jesd204_phy_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 

diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl

diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl

diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl

diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl

diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/scripts/generate_presets.py b/library/jesd204/ad_ip_jesd204_tpl_dac/scripts/generate_presets.py
@@ -43,7 +43,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 ###############################################################################
 
 import math

diff --git a/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl b/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl

diff --git a/library/jesd204/axi_jesd204_common/jesd204_up_common.v b/library/jesd204/axi_jesd204_common/jesd204_up_common.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v b/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 set script_dir [file dirname [info script]]
 

diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2017-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
 set core_clk [get_clocks -of_objects [get_ports core_clk]]

diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 

diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl

diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2019-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 <: setFileUsedIn { out_of_context synthesis implementation } :>
 <: ;#Component and file information :>

diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v b/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v b/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v b/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 set script_dir [file dirname [info script]]
 

diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2017-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
 set core_clk [get_clocks -of_objects [get_ports core_clk]]

diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 

diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl

diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2019-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 <: setFileUsedIn { out_of_context synthesis implementation } :>
 <: ;#Component and file information :>

diff --git a/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v b/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/interfaces/interfaces_ip.tcl b/library/jesd204/interfaces/interfaces_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl

diff --git a/library/jesd204/jesd204_common/jesd204_common_ip.tcl b/library/jesd204/jesd204_common/jesd204_common_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl

diff --git a/library/jesd204/jesd204_common/jesd204_crc12.v b/library/jesd204/jesd204_common/jesd204_crc12.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/jesd204_common/jesd204_eof_generator.v b/library/jesd204/jesd204_common/jesd204_eof_generator.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/jesd204_common/jesd204_frame_align_replace.v b/library/jesd204/jesd204_common/jesd204_frame_align_replace.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 // Limitations:
 //   DATA_PATH_WIDTH = 4, 8

diff --git a/library/jesd204/jesd204_common/jesd204_frame_mark.v b/library/jesd204/jesd204_common/jesd204_frame_mark.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 // Limitations:
 //  for DATA_PATH_WIDTH = 4, 8

diff --git a/library/jesd204/jesd204_common/jesd204_lmfc.v b/library/jesd204/jesd204_common/jesd204_lmfc.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/jesd204_common/jesd204_scrambler.v b/library/jesd204/jesd204_common/jesd204_scrambler.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/jesd204_common/jesd204_scrambler_64b.v b/library/jesd204/jesd204_common/jesd204_scrambler_64b.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/jesd204_common/pipeline_stage.v b/library/jesd204/jesd204_common/pipeline_stage.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/jesd204_common/sync_header_align.v b/library/jesd204/jesd204_common/sync_header_align.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2021-2023, Analog Devices, Inc.
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/jesd204_rx/align_mux.v b/library/jesd204/jesd204_rx/align_mux.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/jesd204_rx/bd/bd.tcl b/library/jesd204/jesd204_rx/bd/bd.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 proc init {cellpath otherInfo} {
   set ip [get_bd_cells $cellpath]

diff --git a/library/jesd204/jesd204_rx/elastic_buffer.v b/library/jesd204/jesd204_rx/elastic_buffer.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 

diff --git a/library/jesd204/jesd204_rx/error_monitor.v b/library/jesd204/jesd204_rx/error_monitor.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps