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1. UFAW2024_content_analysis UFAW2024_content_analysis Public

   An analysis of how different types of animals (farmed, wild, companion, ...) were represented at the UFAW animal welfare conference 2024.

   Python

2. simple_superscalar_out-of-order_pipeline simple_superscalar_out-of-order_pipeline Public

   A superscalar and out-of-order instruction pipeline loosely based on the RISC-V ISA implemented in SystemVerilog.

   SystemVerilog

3. cache_timing cache_timing Public

   In this simple demo I show how one can indirectly access memory content by timing memory accesses.

   C++ 1

4. testbench_generator_for_SystemVerilog_modules testbench_generator_for_SystemVerilog_modules Public

   Takes a SystemVerilog module and creates a skeleton for a testbench. It parses the modport list and creates an instance in the testbench as well as some other useful stuff.

   Python

5. simple_logic_circuit_simulator simple_logic_circuit_simulator Public

   A simple console-based simulator for idealised logic circuits. This was my final project for a C++ course at the University of Manchester.

   C++

6. EA-Sheffield/EA-Sheffield.github.io EA-Sheffield/EA-Sheffield.github.io Public

   HTML