Gitlab CI: enable the SYCL FPGA emulation backend #2471
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| @@ -115,6 +115,10 @@ if [ "${alpaka_ACC_SYCL_ENABLE}" == "OFF" ]; then | |||
| echo_yellow "<DEFAULT: SYCL environment variables for disabled backend>" | |||
| export alpaka_SYCL_ONEAPI_CPU=${alpaka_SYCL_ONEAPI_CPU:=""} | |||
| export alpaka_SYCL_ONEAPI_CPU_ISA=${alpaka_SYCL_ONEAPI_CPU_ISA:=""} | |||
| export alpaka_SYCL_ONEAPI_FPGA=${alpaka_SYCL_ONEAPI_FPGA:=""} | |||
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Can you please add a TODO that this should be split in a separate Intel SYCL CPU and FPGA job in future with the next commit.
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Sure, I can do that, but do you prefer to merge it like this with a TODO, or to actually split it ?
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Like here:
alpaka/script/job_generator/generate_job_yaml.py
Lines 287 to 290 in eca2cd5
The name is optional in general but in this case you can use my one. I use grep to find TODOs.
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Sure, I understand that :-)
What I meant to ask is: are we OK to merge this PR as-is (plus the TODO comment), given that it breaks the SYCL CPU workflows ?
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No, please not. I think you missed my question in the mattermost chat yesterday. It is not possible to compile the CPU and FPGA backend in you job. If this is true, I will start to open an new PR and extend the job generator that it can generate separate jobs for SYCL CPU and FPGA backend.
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I agree we should not merge this PR as-is, without splitting the CPU and FPGA workflows (or finding another solution).
Then I don't understand the reason for the TODO: by the time we do merge it, the split will have been done.
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Then I don't understand the reason for the TODO: by the time we do merge it, the split will have been done.
I was not sure, what is the way to go. You did not directly answer on my question on mattermost and you wrote that you asked Intel. So I was not sure how to continue and I thought better document it, before forget it.
| @@ -391,6 +391,10 @@ def job_variables(job: Dict[str, Tuple[str, str]]) -> Dict[str, str]: | |||
| variables["ALPAKA_CI_ONEAPI_VERSION"] = job[DEVICE_COMPILER][VERSION] | |||
| variables["alpaka_SYCL_ONEAPI_CPU"] = "ON" | |||
| variables["alpaka_SYCL_ONEAPI_CPU_ISA"] = "avx2" | |||
| variables["alpaka_SYCL_ONEAPI_FPGA"] = "ON" | |||
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Can you please add a TODO that this should be split in a separate Intel SYCL CPU and FPGA job in future with the next commit.
Install the oneAPI FPGA support libraries and enable the FPGA back-end in emulator mode.