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1. 32-bit-Risc-Processor 32-bit-Risc-Processor Public

   This repo has all the files needed for simulation of a 32-bit RISC processor, which is built based on 5 stages of pipeline that can handle Arithmetic, logical and load-store operations for now.

   Verilog

2. Design-and-Verification-of-SPI-protocol Design-and-Verification-of-SPI-protocol Public

   Design and Verification of SPI protocol

   SystemVerilog

3. Elevator-design-using-FSM Elevator-design-using-FSM Public

   Design and simulation of FSM based Elevator in Xilinx Vivado

   Verilog 1

4. Master-Slave-D-Flip-Flop Master-Slave-D-Flip-Flop Public

5. Secret-media-enryption-and-decryption-over-image Secret-media-enryption-and-decryption-over-image Public

   B.tech Mini project

   MATLAB 1

6. Synchronous-FIFO Synchronous-FIFO Public

   Verilog