RAM inference transform

alainmarcel · Jan 8, 2024 · 0936d05 · 0936d05
1 parent f1e9d4d
commit 0936d05
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Showing 26 changed files with 7 additions and 111,088 deletions.
diff --git a/tests/PatternAssignment/PatternAssignment.log b/tests/PatternAssignment/PatternAssignment.log
@@ -229,13 +229,6 @@ design: (work@dut)
   \_logic_net: (work@dut.test), line:9:7, endln:9:11
     |vpiParent:
     \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PatternAssignment/dut.sv, line:1:1, endln:15:10
-    |vpiTypespec:
-    \_ref_typespec: (work@dut.test)
-      |vpiParent:
-      \_logic_net: (work@dut.test), line:9:7, endln:9:11
-      |vpiFullName:work@dut.test
-      |vpiActual:
-      \_logic_typespec: , line:9:1, endln:9:18
     |vpiName:test
     |vpiFullName:work@dut.test
     |vpiNetType:36
@@ -476,7 +469,6 @@ design: (work@dut)
 \_logic_typespec: , line:9:1, endln:9:6
   |vpiParent:
   \_logic_var: (work@dut.test), line:9:7, endln:9:18
-\_logic_typespec: , line:9:1, endln:9:18
 \_operation: , line:11:7, endln:11:33
   |vpiParent:
   \_operation: , line:10:12, endln:13:2

diff --git a/tests/SignedVsUnsignedPort/SignedVsUnsignedPort.log b/tests/SignedVsUnsignedPort/SignedVsUnsignedPort.log
@@ -152,13 +152,6 @@ design: (work@dut)
   \_logic_net: (work@dut.rs2_ext_in), line:8:25, endln:8:35
     |vpiParent:
     \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedVsUnsignedPort/dut.sv, line:6:1, endln:12:10
-    |vpiTypespec:
-    \_ref_typespec: (work@dut.rs2_ext_in)
-      |vpiParent:
-      \_logic_net: (work@dut.rs2_ext_in), line:8:25, endln:8:35
-      |vpiFullName:work@dut.rs2_ext_in
-      |vpiActual:
-      \_logic_typespec: , line:8:4, endln:8:23
     |vpiName:rs2_ext_in
     |vpiFullName:work@dut.rs2_ext_in
     |vpiNetType:36
@@ -387,28 +380,6 @@ design: (work@dut)
       |vpiSize:64
       |UINT:0
       |vpiConstType:9
-\_logic_typespec: , line:8:4, endln:8:23
-  |vpiRange:
-  \_range: , line:8:17, endln:8:23
-    |vpiParent:
-    \_logic_typespec: , line:8:4, endln:8:23
-    |vpiLeftRange:
-    \_constant: , line:8:18, endln:8:20
-      |vpiParent:
-      \_range: , line:8:17, endln:8:23
-      |vpiDecompile:32
-      |vpiSize:64
-      |UINT:32
-      |vpiConstType:9
-    |vpiRightRange:
-    \_constant: , line:8:21, endln:8:22
-      |vpiParent:
-      \_range: , line:8:17, endln:8:23
-      |vpiDecompile:0
-      |vpiSize:64
-      |UINT:0
-      |vpiConstType:9
-  |vpiSigned:1
 \_logic_typespec: , line:3:12, endln:3:24
   |vpiRange:
   \_range: , line:3:18, endln:3:24

diff --git a/tests/SimpleClass1/SimpleClass1.log b/tests/SimpleClass1/SimpleClass1.log
diff --git a/tests/SimpleInterface/SimpleInterface.log b/tests/SimpleInterface/SimpleInterface.log
diff --git a/tests/UnboundForLoop/UnboundForLoop.log b/tests/UnboundForLoop/UnboundForLoop.log
@@ -220,13 +220,6 @@ design: (work@signed_shifter)
   \_logic_net: (work@signed_shifter.j), line:4:11, endln:4:12
     |vpiParent:
     \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
-    |vpiTypespec:
-    \_ref_typespec: (work@signed_shifter.j)
-      |vpiParent:
-      \_logic_net: (work@signed_shifter.j), line:4:11, endln:4:12
-      |vpiFullName:work@signed_shifter.j
-      |vpiActual:
-      \_integer_typespec: , line:4:3, endln:4:10
     |vpiName:j
     |vpiFullName:work@signed_shifter.j
   |vpiPort:
@@ -748,8 +741,6 @@ design: (work@signed_shifter)
       |UINT:0
       |vpiConstType:9
   |vpiSigned:1
-\_integer_typespec: , line:4:3, endln:4:10
-  |vpiSigned:1
 ===================
 [  FATAL] : 0
 [ SYNTAX] : 0
@@ -758,5 +749,5 @@ design: (work@signed_shifter)
 [   NOTE] : 5
 
 ============================== Begin RoundTrip Results ==============================
-[roundtrip]: ${SURELOG_DIR}/tests/UnboundForLoop/dut.sv | ${SURELOG_DIR}/build/regression/UnboundForLoop/roundtrip/dut_000.sv | 5 | 8 |
+[roundtrip]: ${SURELOG_DIR}/tests/UnboundForLoop/dut.sv | ${SURELOG_DIR}/build/regression/UnboundForLoop/roundtrip/dut_000.sv | 6 | 8 |
 ============================== End RoundTrip Results ==============================
diff --git a/third_party/UHDM b/third_party/UHDM
diff --git a/third_party/tests/AmiqEth/AmiqEth.log b/third_party/tests/AmiqEth/AmiqEth.log
diff --git a/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log b/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log
diff --git a/third_party/tests/BuildUVMPkg/BuildUVMPkg.log b/third_party/tests/BuildUVMPkg/BuildUVMPkg.log
diff --git a/third_party/tests/CoresSweRV/CoresSweRV.log b/third_party/tests/CoresSweRV/CoresSweRV.log
diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
diff --git a/third_party/tests/Driver/Driver.log b/third_party/tests/Driver/Driver.log
diff --git a/third_party/tests/Ibex/Ibex.log b/third_party/tests/Ibex/Ibex.log
diff --git a/third_party/tests/IbexGoogle/IbexGoogle.log b/third_party/tests/IbexGoogle/IbexGoogle.log
diff --git a/third_party/tests/IncompTitan/IncompTitan.log b/third_party/tests/IncompTitan/IncompTitan.log
@@ -6538,6 +6538,4 @@ var_select                                           882
 [LINT]: ${SURELOG_DIR}/third_party/tests/IncompTitan/src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv:47:16: Unsupported typespec, lc_ctrl_pkg::lc_tx_t
 [LINT]: ${SURELOG_DIR}/third_party/tests/IncompTitan/src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv:48:16: Unsupported typespec, lc_ctrl_pkg::lc_flash_rma_seed_t
 [LINT]: ${SURELOG_DIR}/third_party/tests/IncompTitan/src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv:49:16: Unsupported typespec, lc_ctrl_pkg::lc_tx_t
-[LINT]: ${SURELOG_DIR}/third_party/tests/IncompTitan/src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv:194:3: Unsupported typespec, lc_ctrl_pkg::lc_tx_t
-[LINT]: ${SURELOG_DIR}/third_party/tests/IncompTitan/src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv:195:3: Unsupported typespec, lc_ctrl_pkg::lc_tx_t
 ============================== End Linting Results ==============================