ROHD Hardware Component Libary

A hardware component library developed with ROHD. This library aims to collect a set of reusable, configurable components that can be leveraged in other designs. These components are also intended as good examples of ROHD hardware implementations.

This project is a work in progress! Initial components are primarily focused on correctness, and there is room for optimization from there. Please feel free to contribute or provide feedback. Check out CONTRIBUTING for details on how to contribute.

This project is not intended to be the only place for reusable hardware components developed in ROHD. It's not even intended to be the only library. Contributions are welcomed to this library, but developers are also welcome to build independent packages or libraries, even if they may overlap.

Guidelines for Components

• All components should be Modules so that they are convertible to SystemVerilog
• Components should be general and easily reusable
• Components should be as configurable as may be useful
• Components must be extensively tested
• Components must have excellent documentation and examples
• The first component in a category should be the simplest
• Focus on breadth of component types before depth in one type
• Add extensions to other classes to make component usage easier, when appropriate

Component List

Below is a list of components either already or planning to be implemented.

Marking	Status
No link	Idea phase / included in parent link
Link (OPEN)	An issue is opened for discussion
Link (WIP)	An issue is actively being developed
Link to API	Implemented with API documentation

• Encoders
  • 1-hot to Binary
  • Binary to 1-hot
  • Gray to Binary
  • Binary to Gray
  • Priority
  • PLAs
• Arbiters
  • Priority
  • Round-robin (WIP)
• FIFO
  • Synchronous
  • Asynchronous
  • Bubble Generating
  • Shift register
• Find
  • Find N'th bit (0 or 1) from the start/end (WIP)
  • Min
  • Max
  • Find pattern
• Count
  • Count bit=X
  • Count pattern
• Sort
• Arithmetic
  • Prefix Trees (WIP)
  • Adders
  • Subtractors
  • Multipliers
    • Pipelined Integer Multiplier
  • Dividers
  • Log
  • Square root
  • Inverse square root
  • Floating point
    • Double (64-bit)
    • Float (32-bit)
    • BFloat16 (16-bit)
    • BFloat8 (8-bit)
    • BFloat4 (4-bit)
    • Dot product
• Rotate
  • Dynamic and fixed amounts
  • Left and right
  • Includes extensions on Logic and LogicValue
• Counters
  • Binary counter
  • Gray counter
• LFSR (WIP)
• Error checking
  • ECC
  • CRC
  • Parity
• Data flow
  • Ready/Valid
  • Connect/Disconnect (e.g. SFI)
  • Widening
  • Narrowing
  • Crediting
  • NoC's
    • Coherent
    • Non-Coherent
• Memory
  • Masks
  • Register Files
    • Flop-based
    • Latch-based
  • Replacement Policies
    • LRU
  • Memory Models
• Standard interfaces
  • AXI
  • APB
  • AHB
  • SFI
  • PCIe
  • UCIe
  • JTAG
  • SPI
  • UART
  • DDR
  • HBM

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2023 March 30
Author: Max Korbel <max.korbel@intel.com>

Copyright (C) 2023 Intel Corporation
SPDX-License-Identifier: BSD-3-Clause