ARVI

A simple single cycle RISC-V implementation in SystemVerilog.

Project now

The project is a single-cycle processor implementing RV32I[M][A] instruction set and it also has partial support to RISC-V's machine mode. The project also has a dual core mode (RV32A is necessary). Check rtl/arvi_defines.vh to see all different parameters ARVI can receive.

Besides the processor, the project contains a Performance Profiler to profile each executed program in simulation and retrieve information like how many instructions were issued, cache hits, and misses.

Features

1. Single Cycle RV32I[M][A] RISC-V.
2. Instruction cache.
3. Machine mode privilege level support.
4. Performance Profiler.
5. FPGA Synthesis Script.

Next steps

1. Build pipeline.
2. Implement a bus like Wishbone or AXI to communicate with other devices. At the moment only a simple bus is used.

Project dependencies

1. verilator
2. riscv-fesvr
3. Pyhton3
4. Vivado - Used in synthesis

Make commands

all

$make all

Compile necessary files to create an executable Verilator program.

regression-tests

$make regression-tests

Run all tests in tb/tests.

benchmark

$make benchmark

Run all benchmarks in tb/tests. All benchmarks are from riscv-tests repository and they are already compiled with minor modifications in their source codes.

performance

$make performance

Retrieve all information in all ".performance_report" files in the project and put them into a file named dataframe.csv. You can use this file to check performance parameters of an executed program.

Command line arguments

When compiled using verilator, a executable program is generated. Below are shown the different arguments the program can receive. You can use it as a simple simulator.

-v

Generates a VCD file. No vcd file is generated by default.

-r

Generates a performance report of the executed program. The reports contains information about the number of cycles to run the entire program, and instructions executed per hart. No report is generated by default.

+max-cycles=

Max number of cycles that the processor will run.

+loadmem=

Elf file to be loaded. This parameter must be passed.

--report-output=

Specifies a path to the performance report. This flag must be used with the -r flag.

--no-print

The simulator will not print any message.