CompArchProject
This project was part of the bachelor course "Computer Architecure and trusted computing" at University of Basel. We implemented a classical caluculator from scratch (gates level) on the "Basys 3 Artix-7 FPGA" using Verilog. We have addition, substraction, multiplication, XOR and NAND operations. Each input is 8 bits long (binary) and the output is displayed on a 4 digit long seven-segment display (as hexadecimal) and on 16 LED's (as binary). More details can be viewed in our report file, as well as in the user manual in the docs folder.
Owner: Severin Memmishofer, Yash Trivedi