上海交通大学
数字系统设计课程 Verilog HDL设计电路
包括平时课程训练的组合逻辑电路，时序逻辑电路和大作业的题目代码
以及RISC架构的CPU设计并计算斐波那契数列的实现
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code for course IS208 (Digital System Design) in SJTU
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