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[AIE2/2P] Fix DONE latency at region end. #345

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[AIE2/2P] Fix DONE latency at region end. #345

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9 changes: 9 additions & 0 deletions llvm/lib/Target/AIE/AIE2InstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1172,6 +1172,15 @@ bool AIE2InstrInfo::isLock(unsigned Opc) const {
return false;
}

bool AIE2InstrInfo::isDone(unsigned Opc) const { return Opc == AIE2::DONE; }

unsigned AIE2InstrInfo::getImplicitLatency(const MachineInstr &MI) const {
if (isDone(MI.getOpcode()))
return 6;

return 0;
}

bool AIE2InstrInfo::isDelayedSchedBarrier(const MachineInstr &MI) const {
return MI.getOpcode() == AIE2::DelayedSchedBarrier;
}
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4 changes: 4 additions & 0 deletions llvm/lib/Target/AIE/AIE2InstrInfo.h
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Expand Up @@ -28,6 +28,9 @@
namespace llvm {

class AIE2InstrInfo : public AIE2GenInstrInfo {

bool isDone(unsigned Opc) const override;

public:
AIE2InstrInfo();

Expand Down Expand Up @@ -64,6 +67,7 @@ class AIE2InstrInfo : public AIE2GenInstrInfo {
unsigned getGenericBroadcastVectorOpcode() const override;
unsigned getCycleSeparatorOpcode() const override;
bool isLock(unsigned Opc) const override;
unsigned getImplicitLatency(const MachineInstr &) const override;
bool isDelayedSchedBarrier(const MachineInstr &MI) const override;
bool isSchedBarrier(const MachineInstr &MI) const override;

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9 changes: 9 additions & 0 deletions llvm/lib/Target/AIE/AIEBaseInstrInfo.h
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Expand Up @@ -176,6 +176,15 @@ struct AIEBaseInstrInfo : public TargetInstrInfo {
}
/// Check whether Opc represents a lock instruction
virtual bool isLock(unsigned Opc) const { return false; }

/// Check whether Opc represents a DONE instruction
virtual bool isDone(unsigned Opc) const { return false; }
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nit: I hope no one needs to call this from outside. This one could go and instances could be private or inlined.

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made private.

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I think we can have a design where we need just one method to be reimplemented. Something like:

virtual std::optional<unsigned> getDoneLatency(...)

In this case, we can have a base implementation for getImplicitLatency that can be reimplemented by the target only if needed.

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@andcarminati, The idea was to have a more generic name excluding 'Done'. It's basically an extra latency that can be given to the exit edge. But yes, we would only have one generic method that fills it in.

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Hi, my idea is to avoid encode the latency knowledge separately. If we have a new done, we have two places to change.

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@SagarMaheshwari99 SagarMaheshwari99 Feb 14, 2025 •
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The aim was to encode all "special latencies" into one "getImplicitLatency", so that we don't touch AIEBaseSubTarget frequently. Is there another way other than having a separate function for Opcode to achieve all in one getImplicitLatency?

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@andcarminati andcarminati Feb 14, 2025 •
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Just as a suggestion, I was thinking in something like:

// Return an optional latency if Opc is a done instruction.
std::optional<unsigned>AIE2InstrInfo::getDoneLatency(unsigned Opc) const {
 return (Opc == AIE2::DONE) ? 6 : std::nullopt
}

// This can be in the base class.
unsigned AIE2InstrInfo::getImplicitLatency(const MachineInstr &MI) const {
  if (auto OptLatency = getDoneLatency(MI.getOpcode()))
    return *OptLatency;

  return 0;
}

New targets can just implement getDoneLatency which will encode opcode + latency in the same place.

As I said, just a suggestion to have a single source of information here.


/// Get "implicit" latency for special instructions.
/// This is basically an extra latency, implicit to a special instruction like
/// "DONE", that we would like to give to the exit edge.
virtual unsigned getImplicitLatency(const MachineInstr &) const { return 0; }
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Can you document what that means?

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done.


/// Check whether this is a delayed scheduling barrier induced from
/// a preceding instruction with delay slots.
virtual bool isDelayedSchedBarrier(const MachineInstr &) const {
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4 changes: 4 additions & 0 deletions llvm/lib/Target/AIE/AIEBaseSubtarget.cpp
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Expand Up @@ -282,6 +282,10 @@ class RegionEndEdges : public ScheduleDAGMutation {
EdgeLatency = DelaySlots + 1;
}

// "Implicit" latency for special instructions.
const unsigned ImplicitLatency = TII->getImplicitLatency(MI);
EdgeLatency = std::max(EdgeLatency, ImplicitLatency);
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FYI @mludevid you might have done something similar when working on semaphores.


// Between writing ZOL Registers (lc, le, ls) and the end of the loop,
// there must be a minimum distance. This is ultimately padded out by the
// alignment pass using bundle elongation, but this needs to have enough
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9 changes: 9 additions & 0 deletions llvm/lib/Target/AIE/aie2p/AIE2PInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1219,6 +1219,15 @@ bool AIE2PInstrInfo::isLock(unsigned Opc) const {
return false;
}

bool AIE2PInstrInfo::isDone(unsigned Opc) const { return Opc == AIE2P::DONE; }

unsigned AIE2PInstrInfo::getImplicitLatency(const MachineInstr &MI) const {
if (isDone(MI.getOpcode()))
return 6;

return 0;
}

bool AIE2PInstrInfo::isDelayedSchedBarrier(const MachineInstr &MI) const {
return MI.getOpcode() == AIE2P::DelayedSchedBarrier;
}
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4 changes: 4 additions & 0 deletions llvm/lib/Target/AIE/aie2p/AIE2PInstrInfo.h
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Expand Up @@ -26,6 +26,9 @@
namespace llvm {

class AIE2PInstrInfo : public AIE2PGenInstrInfo {

bool isDone(unsigned Opc) const override;

public:
AIE2PInstrInfo();

Expand Down Expand Up @@ -64,6 +67,7 @@ class AIE2PInstrInfo : public AIE2PGenInstrInfo {
unsigned getGenericVShiftOpcode() const override;
unsigned getGenericExtractSubvectorOpcode() const override;
bool isLock(unsigned Opc) const override;
unsigned getImplicitLatency(const MachineInstr &) const override;
bool isDelayedSchedBarrier(const MachineInstr &MI) const override;
bool isSchedBarrier(const MachineInstr &MI) const override;

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29 changes: 29 additions & 0 deletions llvm/test/CodeGen/AIE/schedule/done.mir
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@@ -0,0 +1,29 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
#
# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
# See https://llvm.org/LICENSE.txt for license information.
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
#
# (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates

# RUN: llc -march=aie2 --issue-limit=6 --aie-bottomup-cycles=0 -run-pass=postmisched %s -o - | FileCheck %s
# RUN: llc -march=aie2p --issue-limit=6 --aie-bottomup-cycles=0 -run-pass=postmisched %s -o - | FileCheck %s

# Check 6 cycle latency at region end.
---
name: done
body: |
bb.0.entry:
; CHECK-LABEL: name: done
; CHECK: SCHED_BARRIER
; CHECK-NEXT: DONE
; CHECK-NEXT: NOP
; CHECK-NEXT: NOP
; CHECK-NEXT: NOP
; CHECK-NEXT: NOP
; CHECK-NEXT: NOP
; CHECK-NEXT: SCHED_BARRIER
SCHED_BARRIER
DONE
SCHED_BARRIER
...