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VERA PSG: implement 9 bit volume table/Verilog changes #481

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Triggered via pull request March 20, 2024 05:38

mooinglemur

opened #254

mooinglemur:20240319-psg-volres

Status Success

Total duration 7m 20s

Artifacts 8

build.yml

on: pull_request

build-win-x86_64

build-linux-x86_64

build-linux-aarch64

build-linux-armhf

build-macos-x86_64

Artifacts

Produced during runtime

Name	Size
readme-pdf Expired	538 KB
x16emu_linux-aarch64 Expired	3.78 MB
x16emu_linux-armhf Expired	3.65 MB
x16emu_linux-x86_64 Expired	3.84 MB
x16emu_macos Expired	4.5 MB
x16emu_wasm Expired	515 KB
x16emu_win32 Expired	4.79 MB
x16emu_win64 Expired	4.76 MB