versal: integrate LPD SLCR registers into versal

Realize the low power domain system level control
registers as part of Versal SoC and map the control
registers into the PS address space.

Signed-off-by: Nelson Ho <Nelson.Ho@windriver.com>

hw/arm/xlnx-versal.c

@@ -806,6 +806,21 @@ static void versal_create_smmu(Versal *s, qemu_irq *pic)
     sysbus_connect_irq(sbd, 0, pic[VERSAL_SMMU_IRQ]);
 }
 
+static void versal_create_lpd_slcr(Versal *s)
+{
+    SysBusDevice *sbd;
+    MemoryRegion *mr;
+
+    object_initialize_child(OBJECT(s), "lpd_slcr", &s->lpd.slcr,
+                            TYPE_XILINX_LPD_SLCR);
+    sbd = SYS_BUS_DEVICE(&s->lpd.slcr);
+    sysbus_realize(sbd, &error_fatal);
+
+    mr = sysbus_mmio_get_region(sbd, 0);
+
+    memory_region_add_subregion(&s->mr_ps, MM_LPD_SLCR, mr);
+}
+
 /* This takes the board allocated linear DDR memory and creates aliases
  * for each split DDR range/aperture on the Versal address map.
  */
@@ -948,6 +963,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
     versal_create_efuse(s, pic);
     versal_create_pmc_iou_slcr(s, pic);
     versal_create_ospi(s, pic);
+    versal_create_lpd_slcr(s);
     versal_create_crl(s, pic);
     versal_create_cfu(s, pic);
     versal_map_ddr(s);

include/hw/arm/xlnx-versal.h

@@ -29,6 +29,7 @@
 #include "hw/nvram/xlnx-versal-efuse.h"
 #include "hw/ssi/xlnx-versal-ospi.h"
 #include "hw/dma/xlnx_csu_dma.h"
+#include "hw/misc/xlnx-versal-lpd-slcr.h"
 #include "hw/misc/xlnx-versal-crl.h"
 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
 #include "hw/misc/xlnx-versal-trng.h"
@@ -102,6 +103,7 @@ struct Versal {
         } xram;
 
         XlnxVersalCRL crl;
+        LPD_SLCR slcr;
     } lpd;
 
     /* The Platform Management Controller subsystem.  */
@@ -224,6 +226,8 @@ struct Versal {
 #define MM_PSM_START                0xffc80000U
 #define MM_PSM_END                  0xffd00000U
 
+#define MM_LPD_SLCR                 0xff410000U
+
 #define MM_CRL                      0xff5e0000U
 #define MM_CRL_SIZE                 0x300000
 #define MM_IOU_SCNTR                0xff130000U