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Fixed clock alignment in axi_stream_master vc #420

Merged
merged 4 commits into from
Dec 10, 2018
Merged

Fixed clock alignment in axi_stream_master vc #420

merged 4 commits into from
Dec 10, 2018

Commits on Dec 10, 2018

  1. Split axi stream master process into two separate processes, as was d… 

    …one in axi_lite_master before, to keep alignment with the clock edge and make it possible to implement a wait_until_idle. After handling a wait_for_time message, there is a realignment with the clock as well. To still be able to run at full speed, the queue is processed until it is empty before waiting for another rising edge.

Added an extra test to the testbench to verify clock alignment.
Slightly modified other tests according to changed timing behavior.
Added 'wait until idle' to pop before push test to verify it's behavior.
    Olaf van den Berg committed Dec 10, 2018
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  2. removed whitespaces and extra empty line

    Olaf van den Berg committed Dec 10, 2018
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  3. added delete of msg after it was handled and before a new msg is popp… 

    …ed from the queue
    Olaf van den Berg committed Dec 10, 2018
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  4. wait for valid to become 1, so that "not_valid" checks do not interfe… 

    …re with mocked checks.

Apparently there is a difference between GHDL and modelsim in this aspect.
Modelsim simulation passed without waiting on tvalid='1' and just an extra 'wait until rising_edge(aclk)', ghdl needs more.
    Olaf van den Berg committed Dec 10, 2018
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