All aarch64 Instructions by Category

All aarch64 instructions by category

Legend:

• ➖ (:heavy_minus_sign): unimplemented
• ✅ (:white_check_mark:): mark implemented instructions
• 🔜 (:soon:) for partially implemented instructions
• ❌ (:x:) to mark ones we can't implement
• ❓ (:question:) to raise issues

Abbreviations:

• imm: immediate
• shift: shifted register
• reg: register
• ext: extended register
• vec: vector

Indented dot-points indicate aliases of the parent instruction. LLVM automatically de-aliases these, so we only need to worry about implementing the top-level dot points.

Moves, stores, loads

Instructions	Status
LDADD, LDADDA, LDADDAL, LDADDL STADD, STADDL	➖
LDADDB, LDADDAB, LDADDALB, LDADDLB STADDB, STADDLB	➖
LDADDH, LDADDAH, LDADDALH, LDADDLH STADDH, STADDLH	➖
LDAPR	➖
LDAPRB	➖
LDAPRH	➖
LDAPUR	➖
LDAPURB	➖
LDAPURH	➖
LDAPURSB	➖
LDAPURSH	➖
LDAPURSW	➖
LDAR	➖
LDARB	➖
LDARH	➖
LDAXP	➖
LDAXR	➖
LDAXRB	➖
LDAXRH	➖
LDCLR, LDCLRA, LDCLRAL, LDCLRL STCLR, STCLRL	➖
LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB STCLRB, STCLRLB	➖
LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH STCLRH, STCLRLH	➖
LDEOR, LDEORA, LDEORAL, LDEORL STEOR, STEORL	➖
LDEORB, LDEORAB, LDEORALB, LDEORLB STEORB, STEORLB	➖
LDEORH, LDEORAH, LDEORALH, LDEORLH STEORH, STEORLH	➖
LDLAR	➖
LDLARB	➖
LDLARH	➖
LDNP	➖
LDP	🔜
LDPSW	➖
LDR (imm)	🔜
LDR (literal)	➖
LDR (reg)	✅
LDRB (imm)	✅
LDRB (reg)	✅
LDRH (imm)	🔜
LDRH (reg)	✅
LDRSB (imm)	➖
LDRSB (reg)	➖
LDRSH (imm)	➖
LDRSH (reg)	➖
LDRSW (imm)	➖
LDRSW (literal)	➖
LDRSW (reg)	✅
LDSET, LDSETA, LDSETAL, LDSETL STSET, STSETL	➖
LDSETB, LDSETAB, LDSETALB, LDSETLB STSETB, STSETLB	➖
LDSETH, LDSETAH, LDSETALH, LDSETLH STSETH, STSETLH	➖
LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL STSMAX, STSMAXL	➖
LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB STSMAXB, STSMAXLB	➖
LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH STSMAXH, STSMAXLH	➖
LDSMIN, LDSMINA, LDSMINAL, LDSMINL STSMIN, STSMINL	➖
LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB STSMINB, STSMINLB	➖
LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH STSMINH, STSMINLH	➖
LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL STUMAX, STUMAXL	➖
LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB STUMAXB, STUMAXLB	➖
LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH STUMAXH, STUMAXLH	➖
LDUMIN, LDUMINA, LDUMINAL, LDUMINL STUMIN, STUMINL	➖
LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB STUMINB, STUMINLB	➖
LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH STUMINH, STUMINLH	➖
LDUR	✅
LDURB	✅
LDURH	✅
LDURSB	✅
LDURSH	✅
LDURSW	✅
LDXP	➖
LDXR	➖
LDXRB	➖
LDXRH	➖
MOVK	✅
MOVN MOV (inverted wide imm)	🔜
MOVZ MOV (wide imm)	✅
MRS	➖
MSR (imm)	➖
MSR (reg)	➖
STLLR	➖
STLLRB	➖
STLLRH	➖
STLR	➖
STLRB	➖
STLRH	➖
STLUR	➖
STLURB	➖
STLURH	➖
STLXP	➖
STLXR	➖
STLXRB	➖
STLXRH	➖
STNP	➖
STP	✅
STR (imm)	✅
STR (reg)	✅
STRB (imm)	✅
STRB (reg)	➖
STRH (imm)	➖
STRH (reg)	➖
STUR	✅
STURB	✅
STURH	✅
SWP, SWPA, SWPAL, SWPL	➖
SWPB, SWPAB, SWPALB, SWPLB	➖
SWPH, SWPAH, SWPALH, SWPLH	➖

Logical/bitfield operations

Instructions	Status
AND (imm)	✅
AND (shift)	✅
ANDS (imm) TST (imm)	✅
ANDS (shift) TST (shift)	✅
ASRV ASR (reg)	✅
BFM BFC, BFI, BFXIL	➖
BIC (shift)	✅
BICS (shift)	✅
CLS	➖
CLZ	✅
EON (shift)	➖
EOR (imm)	c
EOR (shift)	✅
EXTR ROR (imm)	➖
LSLV LSL (reg)	✅
LSRV LSR (reg)	✅
ORN (shift) MVN	✅
ORR (imm) MOV (bitmask imm)	✅
ORR (shift) MOV (reg)	✅
RBIT	✅
REV REV64	✅
REV16	➖
REV32	➖
RORV ROR (reg)	✅
SBFM ASR (imm), SBFIZ, SBFX, SXTB, SXTH, SXTW	✅
UBFM LSL (imm), LSR (imm), UBFIZ, UBFX, UXTB, UXTH	✅

Integer arithmetic and related

Instructions	Status
ADC	➖
ADCS	➖
ADD (ext)	✅
ADD (imm) MOV (to/fro SP)	✅
ADD (shift)	✅
ADDG	➖
ADDS (ext) CMN (ext)	✅
ADDS (imm) CMN (imm)	✅
ADDS (shift) CMN (shift)	✅
ADR	✅
ADRP	✅
MADD MUL	✅
MSUB MNEG	✅
SBC NGC	➖
SBCS NGCS	➖
SDIV	✅
SMADDL SMULL	✅
SMSUBL SMNEGL	✅
SUB (ext)	✅
SUB (imm)	✅
SUB (shift) NEG (shift)	✅
SUBP	➖
SUBPS CMPP	➖
SUBS (ext) CMP (ext)	➖
SUBS (imm) CMP (imm)	✅
SUBS (shift) CMP (shift), NEGS	✅
UDIV	✅
UMADDL UMULL	✅
UMSUBL UMNEGL	✅
UMULH	✅

✅ Branch instructions

Instructions	Status
B.cond	✅
B	✅
BL	✅
BLR	✅
BR	✅
CBNZ	✅
CBZ	✅
RET	✅
TBNZ	✅
TBZ	✅

Other atomic operations

Instructions	Status
CAS, CASA, CASAL, CASL	✅
CASB, CASAB, CASALB, CASLB	✅
CASH, CASAH, CASALH, CASLH	✅
CASP, CASPA, CASPAL, CASPL	➖
CSEL	✅
CSINC CINC, CSET	✅
CSINV CINV, CSETM	✅
CSNEG CNEG	✅

❓ Cryptographic instructions

Let's finish the others before getting to these..

Instructions	Status
AESD	➖
AESE	➖
AESIMC	➖
AESMC	➖
CRC32B, CRC32H, CRC32W, CRC32X	➖
CRC32CB, CRC32CH, CRC32CW, CRC32CX	➖
SHA1C	➖
SHA1H	➖
SHA1M	➖
SHA1P	➖
SHA1SU0	➖
SHA1SU1	➖
SHA256H	➖
SHA256H2	➖
SHA256SU0	➖
SHA256SU1	➖
SHA512H	➖
SHA512H2	➖
SHA512SU0	➖
SHA512SU1	➖
SHADD	➖
SM3PARTW1	➖
SM3PARTW2	➖
SMESS1	➖
SM3TT1A	➖
SM3TT1B	➖
SM3TT2A	➖
SM3TT2B	➖
SM4E	➖
SM4EKEY	➖

✅ Processor State Instructions

These are just instructions that specifically deal with processor state. Other ones in other categories modify flags.

Instructions	Status
CCMN (imm)	✅
CCMN (reg)	✅
CCMP (imm)	✅
CCMP (reg)	✅
CFINV	✅
RMIF	✅
SETF8, SETF16	✅

❓ System/security Instructions

Some of these require us to model processor exceptions, privileges etc. Not sure if we're doing that.

Instructions	Status
AUTDA, AUTDZA	➖
AUTDB, AUTDZB	➖
AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA	➖
AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB	➖
BLRAA, BLRAAZ, BLRAB, BLRABZ	➖
BRAA, BRAAZ, BRAB, BRABZ	➖
BTI	➖
CLREX	➖
ERET	➖
ERETAA, ERETAB	➖
GMI	➖
HVC	➖
IRG	➖
LDG	➖
LDGV	➖
LDRAA, LDRAB	➖
LDTR	➖
LDTRB	➖
LDTRH	➖
LDTRSB	➖
LDTRSH	➖
LDTRSW	➖
PACDA, PACZDA	➖
PACDB, PACDZB	➖
PACGA	➖
PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA	➖
PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB	➖
PFRM (imm) [this is cool]	➖
PFRM (literal)	➖
PFRM (reg)	➖
PFRM (unscaled offset)	➖
RETAA, RETAB	➖
SMC	➖
STTR	➖
STTRB	➖
STTRH	➖
STXP	➖
STXR	➖
STXRB	➖
STXRH	➖
STZ2G	➖
STZG	➖
SVC	➖
SYS AT, CFP, CPP, DC, DVP, IC, TLBI	➖
SYSL	➖
XAFlag	➖
XPACD, XPACI, XPACLRI	➖

Special instructions

Instructions	Status
CSDB	➖
DMB	✅
DSB	✅
ESB	➖
HINT	✅
ISB	✅
NOP	➖
PSB CSYNC	➖
PSSBB	➖
SB	➖
SEV	➖
SEVL	➖
SSBB	➖
ST2G	➖
STG	➖
STGP	➖
STGV	➖
SUBG	➖
TSB CSYNC	➖
UDF	✅
WFE	➖
WFI	➖
YIELD	➖

❓ Debug instructions

Not sure how to implement these in Primus Lisp.

Instructions	Status
BRK	➖
DCPS1	➖
DCPS2	➖
DCPS3	➖
DRPS	➖
HLT	➖

❌ FP/Vector/SIMD instructions

I think implementing these is outside the scope of the project, but let me know if I'm wrong.

Instructions	Status
ABS	➖
ADD (vec)	➖
ADDHN, ADDHN2	➖
ADDP (scalar)	➖
ADDP (vec)	➖
ADDV	➖
AND (vec)	➖
AXflag	➖
BCAX	➖
BIC (vec, imm)	➖
BIC (vec, reg)	➖
BIF	➖
BIT	➖
BSL	➖
CLS (vec)	➖
CLZ (vec)	➖
CMEQ (reg)	➖
CMEQ (zero)	➖
CMGE (reg)	➖
CMGE (zero)	➖
CMGT (reg)	➖
CMGT (zero)	➖
CMHI (reg)	➖
CMHS (reg)	➖
CMLE (zero)	➖
CMLT (zero)	➖
CMTST	➖
CNT	➖
DUP (element)	➖
DUP (general)	➖
EOR3	➖
EOR (vec)	➖
EXT	➖
everything starting with F	➖
INS (element) MOV (element)	✅
INS (general) MOV (from general)	✅
LD1 (multiple structures)	✅
LD1 (single structure)	✅
LD1R	✅
LD2 (multiple structures)	✅
LD2 (single structure)	✅
LD2R	✅
LD3 (multiple structures)	✅
LD3 (single structure)	✅
LD3R	✅
LD4 (multiple structures)	✅
LD4 (single structure)	✅
LD4R	✅
LDNP (SIMD&FP)	✅
LDP (SIMD&FP)	✅
LDR (imm, SIMD&FP)	✅
LDR (literal, SIMD&FP)	✅
LDR (reg, SIMD&FP)	✅
LDUR (SIMD&FP)	✅
MLA (by element)	➖
MLA (vec)	➖
MLS (by element)	➖
MLS (vec)	➖
MOVI	➖
MUL (by element)	➖
MUL (vec)	➖
MVNI	➖
NEG (vec)	➖
NOT MVN	➖
ORN (vec)	➖
ORR (vec, imm)	➖
ORR (vec, reg)	➖
PMUL	➖
PMULL, PMULL2	➖
RADDHN, RADDHN2	➖
RAX1	➖
RBIT	➖
REV16 (vec)	➖
REV32 (vec)	➖
REV64	➖
RSHRN, RSHRN2	➖
RSUBHN, RSUBHN2	➖
SABA	➖
SABAL, SABAL2	➖
SABD	➖
SABDL, SABDL2	➖
SADALP	➖
SADDL, SADDL2	➖
SADDLP	➖
SADDLV	➖
SADDW, SADDW2	➖
SCVTF (vec, fixed-point)	➖
SCVTF (vec, integer)	➖
SCVTF (scalar, fixed-point)	➖
SCVTF (scalar, integer)	➖
SDOT (by element)	➖
SDOT (vec)	➖
SHL	➖
SHLL, SHLL2	➖
SHRN, SHRN2	➖
SHSUB	➖
SLI	➖
SMAX	➖
SMAXP	➖
SMAXV	➖
SMIN	➖
SMINP	➖
SMINV	➖
SMLAL, SMLAL2 (by element)	➖
SMLAL, SMLAL2 (vec)	➖
SMLSL, SMLSL2 (by element)	➖
SMLSL, SMLSL2 (vec)	➖
SMOV	➖
SMULL, SMULL2 (by element)	➖
SMULL, SMULL2 (vec)	➖
everything starting with SQ	➖
SRHADD	➖
SRI	➖
SRSHL	➖
SRSHR	➖
SRSRA	➖
SSHL	➖
SSHLL, SSHLL2 SXTL, SXTL2	➖
SSHR	➖
SSRA	➖
SSUBL, SSUBL2	➖
SSUBW, SSUBW2	➖
ST1 (multiple structures)	➖
ST1 (single structure)	➖
ST2 (multiple structures)	➖
ST2 (single structure)	➖
ST3 (multiple structures)	➖
ST3 (single structure)	➖
ST4 (multiple structures)	➖
ST4 (single structure)	➖
STNP (SIMD&FP)	➖
STP (SIMD&FP)	✅
STR (imm, SIMD&FP)	✅
STR (REG, SIMD&FP)	✅
STUR (SIMD&FP)	✅
SUB (vec)	➖
SUBHN, SUBHN2	➖
SUQADD	➖
TBL	➖
TRN1	➖
TRN2	➖
UABA	➖
UABAL, UABAL2	➖
UABD	➖
UABDL, UABDL2	➖
UADALP	➖
UADDL, UADDL2	➖
UADDLP	➖
UADDLV	➖
UADDW, UADDW2	➖
UCVTF (vec, fixed-point)	➖
UCVTF (vec, int)	➖
UCVTF (scalar, fixed-point)	➖
UCVTF (scalar, int)	➖
UDOT (by element)	➖
UDOT (vec)	➖
UHADD	➖
UHSUB	➖
UMAX	➖
UMAXP	➖
UMAXV	➖
UMIN	➖
UMINP	➖
UMINV	➖
UMLAL, UMLAL2 (by element)	➖
UMLAL, UMLAL2 (vec)	➖
UMLSL, UMLSL2 (by element)	➖
UMLSL, UMLSL2 (vec)	➖
UMOV MOV (to general)	➖
UMULL, UMULL2 (by element)	➖
UMULL, UMULL2 (vec)	➖
UQADD	➖
UQRSHL	➖
UQRSHRN, UQRSHRN2	➖
UQSHL (imm)	➖
UQSHL (reg)	➖
UQSHRN, UQSHRN2	➖
UQSUB	➖
UQXTN	➖
UQXTN2	➖
URECPE	➖
Urhadd	➖
URSHL	➖
URSHR	➖
URSQRTE	➖
URSRA	➖
USHL	➖
USHLL, USHLL2 UXTL, UXTL2	➖
USHR	➖
USQADD	➖
USRA	➖
USUBL, USUBL2	➖
USUBW, USUBW2	➖
UZP1	➖
UZP2	➖
XAR	➖
XTN, XTN2	➖
ZIP1	➖
ZIP2	➖

Notes

What are "tags"? They're used by GMI, IRG, LDG, LDGV, ST2G, STG, STGP, STGV, STZ2G, STZG, SUBG.