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RVV: Refine riscv gemm fp32 #5303

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merged 6 commits into from
Jan 30, 2024
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Xinyu302
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@Xinyu302 Xinyu302 commented Jan 22, 2024

Use RVV intrinsic vsseg4e32_v_f32m1, vsseg2e32_v_f32m1 to do load interleaved.
Modify transpose.

@github-actions github-actions bot added the riscv label Jan 22, 2024
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codecov-commenter commented Jan 23, 2024

Codecov Report

All modified and coverable lines are covered by tests ✅

Comparison is base (05b4dcb) 94.19% compared to head (a0f055a) 94.19%.
Report is 8 commits behind head on master.

Additional details and impacted files
@@            Coverage Diff             @@
##           master    #5303      +/-   ##
==========================================
- Coverage   94.19%   94.19%   -0.01%     
==========================================
  Files         777      777              
  Lines      243348   243271      -77     
==========================================
- Hits       229221   229145      -76     
+ Misses      14127    14126       -1     

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@nihui nihui closed this Jan 29, 2024
@nihui nihui reopened this Jan 29, 2024
@nihui nihui merged commit 7ac4268 into Tencent:master Jan 30, 2024
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nihui commented Jan 30, 2024

Thanks for your contribution !

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3 participants