- 🔭 I’m currently working on VLSI Design & Verification domain
- 🌱 I’m currently learning lots of stuff related to advanced verification
- 👯 I’m looking to collaborate on research in VLSI computing , VLSI architecture ,VLSI verification
- 🤔 Enjoy in coding with : Verilog , SV , UVM
- 💬 Goal : Learn & contribute more to open source projects
- 📫 How to reach me: Just drop me an email
- 😄 Pronouns: He/Him
- ⚡ Fun fact: Love to Learn , Unlearn & UnLearn
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Ready to Learn,Unlearn and Relearn
Research Focus (Academia/Industry): VLSI Design & Verification, VLSI Computing, Computer Arithmetic, VLSISP, Communication Protocol Verif.
Popular repositories Loading
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Fundamentals-of-System-Verilog-Part-1
Fundamentals-of-System-Verilog-Part-1 PublicAim to explore the System Verilog concepts with Hands on , which could be used for verification
SystemVerilog 1
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Verilog-Coding-for-VLSI-engineers
Verilog-Coding-for-VLSI-engineers PublicFocus on various hands on examples with neat explanation
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Fundamentals-of-System-Verilog-Part-2
Fundamentals-of-System-Verilog-Part-2 PublicIncludes advance concepts of verification
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