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Ready to Learn,Unlearn and Relearn
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Ready to Learn,Unlearn and Relearn

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Sibakumarpanda/README.md

Hi there , I'm Siba Kumar Panda 👋

  • 🔭 I’m currently working on VLSI Design & Verification domain
  • 🌱 I’m currently learning lots of stuff related to advanced verification
  • 👯 I’m looking to collaborate on research in VLSI computing , VLSI architecture ,VLSI verification
  • 🤔 Enjoy in coding with : Verilog , SV , UVM
  • 💬 Goal : Learn & contribute more to open source projects
  • 📫 How to reach me: Just drop me an email
  • 😄 Pronouns: He/Him
  • ⚡ Fun fact: Love to Learn , Unlearn & UnLearn

Popular repositories Loading

  1. Fundamentals-of-System-Verilog-Part-1 Fundamentals-of-System-Verilog-Part-1 Public

    Aim to explore the System Verilog concepts with Hands on , which could be used for verification

    SystemVerilog 1

  2. test_repo_for_credentials test_repo_for_credentials Public

    1

  3. Sibakumarpanda Sibakumarpanda Public

    Config files for my GitHub profile

    1

  4. D-F-F-Design D-F-F-Design Public

    Verilog

  5. Verilog-Coding-for-VLSI-engineers Verilog-Coding-for-VLSI-engineers Public

    Focus on various hands on examples with neat explanation

  6. Fundamentals-of-System-Verilog-Part-2 Fundamentals-of-System-Verilog-Part-2 Public

    Includes advance concepts of verification